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Intel DFT Lead /Manager India, Karnataka, Bengaluru 348387482
In this position you will be part of a world class DFT team which works on next generation SOCs and IPs. You will be working with a group of highly talented engineers working on cutting edge technologies.As DFT Lead your responsibilities include
- Lead DFT design implementation, validation, post silicon bringup of upcoming Discrete/integrated graphics projects.
- Leading and managing the team responsible for upcoming projects on Graphics IP and SOC design.
- Ensure timely execution and quality goals are met. Review processes and methodologies, suggest updates to drive towards efficiency and Quality.
- Responsible for enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, applying differentiated performance management, and driving team results.
- Drives results by inspiring people, role modeling Intel values, developing the capabilities of others, and ensuring a productive work environment.
- Works at technical level as well including FE/BE leads, Microarchitects, Post-silicon teams
DFT lead will exhibit following traits
- Excellent verbal and written communication and collaboration skills.
- Strong communication and collaboration skills, including a willingness to work with others, and the ability to tolerate ambiguity and highly complex decision environments.
- Willingness to lead teams and influence cross-functional teams.
- Lead by example, Prioritization and collaboration.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through relevant schoolwork, internships, jobs and/or research experience.Minimum skills and Experience:
- Bachelors in Electrical/Computer Engineering or related field with 10+ years of academic or industry experience. Or a Masters in the same fields with 8+ Years of academic or industry experience.
- Your experience should be in the following
- At least one of the key DFT features such as TAP/JTAG, Scan/ATPG or Array DFT (MBIST/PBIST)
- SoC IP DFT design integration or verification
- EDA tools such as ATPG tools, Mentor Tessent shell, VCS simulation and/or debug tools.
- Silicon enabling debug or test pattern development experience
Preferred Skills and Experience
- Managing and leading a technical team.
- Good understanding of the ASIC design flow as well as the DFT and Manufacturing requirements
- Skilled in DFT design and Integration, various validation techniques and industry standard methodologies - IJTAG, MBIST, SCAN, etc.
- Structural design flows, including timing, routing, placement or clocking analysi
- SOC architecture, RTL coding and post silicon debug
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