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Google ASIC SOC DFT Lead Silicon 
India, Karnataka, Bengaluru 
914003345

12.06.2024
Minimum qualifications:
  • Bachelor's degree in Mechanical Engineering, Electrical Engineering, Industrial Engineering, or equivalent practical experience.
  • 8 years of experience in design for testability.
  • Experience with ATPG, low power designs, BIST, JTAG tools and flow.

Preferred qualifications:
  • Experience working on SoC level DFT.
  • Knowledge of high performance design DFT techniques.
  • Understanding of the end to end flows - design, verification, DFT, and PD.
  • Proficiency with Synthesis, Lint, CDC, LEC and DFT timing, and STA.
  • Proficiency with a scripting language such as Perl.