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Apple CAD Engineer - PDV United States, California, Sunnyvale 342558873
18.11.2024
Description
- Develop, improve and maintain various aspects of physical verification flow and methodology- Coordinate the effort of validating flows, improving for custom checks and data generation- Code custom PDV rule decks such as Electrical rule checks (ERC) and Programmable ERCs
Minimum Qualifications
- Previous industry experience in Silicon chip design flows
- Tapeout support and IP/SOC level PDV debug experience in various technology nodes
- Scripting skills in programming languages such as Python, Perl, Tcl, Shell, Makefile or C
- Experience with flow automation and development in advanced nodes
- Minimum requirement of BS and 10+ years of relevant industry experience
Preferred Qualifications
- Knowledge in Calibre/ICV runset coding for DRC/LVS/ERC/MFILL
- Rule coding in PERC is a plus
- Knowledge of parasitic extraction, SKILL coding, and PnR tools is a plus
Pay & Benefits
- At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $175,800 and $312,200, and your base pay will depend on your skills, qualifications, experience, and location.Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
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