In this role you will: - Develop verification plans in coordination with design leads and architects.- Build and maintain portable verification test bench components and environments.- Generate directed and constrained random tests.- Run simulations and debug design and environment issues.- Create functional coverage points, analyze coverage, and improve test environment to target coverage holes.- Create automated verification flows for block verification.- Apply knowledge of hardware description languages (VHDL/Verilog) to verify complex designs.- Work with other block, subsystem and chip level engineers to ensure seamless verification flow.