Nvidia Senior VLSI CAD R&D Power Timing Modeling 

United States, Texas 

325357891

NVIDIA's continued advancement of world-leading hardware requires a combination of the best of both external and internal EDA tools. Our team develops these highly optimized internal tools by fusing advances in silicon modeling, machine learning, and novel algorithms in C++. We are seeking a CAD R&D Engineer excited to innovate in algorithms for large scale and high accuracy gate-level power, timing, parasitic, and noise analysis. A deep understanding of existing Liberty modeling including CCS, CCSP, CCSN, and LVF is required along with the insight to develop new types of models based on silicon feedback. Some experience in parasitic extraction and/or interconnect modeling is also needed. We particularly focus on high performance algorithms, so proficiency in multithreaded code is ideal.

What you’ll be doing:

• Invent and optimize methods to improve the accuracy and capacity of timing, power, and noise models used within a suite of internal optimization tools. These tools already outperform the industry's alternatives in high capacity timing and power optimization and will advance even further with your contributions.

• Develop new ways of modeling device and interconnect physics beyond the capabilities of external EDA tools to better match Vmin and Fmax distributions observed in real silicon.

• Boost the accuracy and efficient application of incremental parasitic estimates used during optimization

• Over time, this role can expand to other areas of physical design implementation and analysis tools

• As with any software engineering team, we do write a lot of code, but this is broader than a typical CAD or EDA role. Instead, we as a team own the whole process from discovery and invention of new optimization opportunities, to developing solutions and working directly inside design teams to facilitate deployment.

What we need to see:

• MS or PhD in Electrical Engineering or Device Physics (or equivalent experience)

• 8+ years experience in gate-level static timing analysis and/or power analysis

• Proficiency in C++

• Strong background of Liberty timing, power, and noise models (CCS, CCSP, CCSN)

• Thorough understanding of interconnect parasitic models and their representation in SPEF

• Good understanding of algorithm design principles such as complexity analysis, efficient memory and I/O use, etc.

Ways to stand out from the crowd:

• Experience with GNNs (Graph Neural Networks) and other relevant machine learning frameworks, especially as applied to device and interconnect modeling

• Expertise in PrimeTime, PrimeTime-PX, NanoTime, SPICE, or other analysis tools

• Background in physical design, timing, and/or power optimization algorithms.

• Experience in mitigating logic glitches in adders and other highly reconvergent logic

• Background in high performance software design including multithreading, distributed computing, and efficient memory use.