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Apple Design Verification Engineer United States, West Virginia 31206466
05.09.2025
- At least 3 years of verification experience
- At least 3 years of verification experience
- Knowledge of Wireless Connectivity or MAC verification is a plus
- Advanced knowledge of standard ASIC design and verification flows, simulation and testbench development
- Advanced knowledge of SystemVerilog and the UVM methodology is highly preferred
- Skills with constrained random testing, coverage closure, gate level simulations
- Experience writing scripts in languages such as Perl or Python
- Team player with excellent communication skills and the desire to take on diverse challenges
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