Amazon Hardware Development Engineer Project Kuiper 

United States, Washington, Redmond 

306467288

Role for Kuiper Sr. RFIC Layout design engineer:
As a Sr. RFIC Layout design engineer, you will be an integral part of the IC design team. Lead layout at a technical level, build circuit layouts for RF controller architectures. You will work in an integral team with the RFIC/Mixed signal designers on full chip layout of custom analog and RFIC designs. Work with the IC designers and chip leads to determine the chip floor plan. This includes strategies for power and ground distribution as well as working with package engineers to determine pad locations. You are required to accurately estimating the schedule for the layout tasks in a timely manner that is trackable, reportable and in sync with project deliverables. You are to identifying areas of complexity that needs early investigation.Perform custom layout of RF and analog circuit blocks with attention to matching and minimizing parasitics in the layout. Requirements include proficiency in Cadence Software (EDA) to develop, test and improve manufacturing processes and product designs for analog circuits. Proficiency in DRCs, ERCs and LVS checks; and resolving errors. Proficiency top-level layout integration with ESD structures and pad assembly; Including density fill, running DFM checks, preparing database for foundry deliveryExport Control Requirement:
Key job responsibilities
In this role you will:
• You will work closely with an internal inter-disciplinary team to drive key aspects of product definition, execution and optimization.
• You must be responsive, flexible and able to succeed within an open collaborative peer environment.
• You are required to specialize in application-specific integrated circuits. Additional requirements include proficiency/expertise in Cadence Software (CAD) to develop, test and improve manufacturing processes and product designs for analog circuits.
• Proficiency in verification software for Design Rule Checks (DRCs) and Layout vs Schematic (LVS) are necessary.
• Perform checks such as multi-patterning, latch-up, ESD, and density
• Required to perform layout in a timely manner that is trackable, reportable and in sync with project schedule
• Collaborate with digital design, and other RFIC design teams to define floorplans for RF front-ends and beamforming ICs.
• Layout high-performance analog, RF and mm-wave circuits keeping in mind requirements for matching, parasitic capacitance, electromigration, and all DRC rules.

• Bachelor's degree in Electrical / Communications Engineering or related field, or equivalent experience
• 7+ years of hands on experience full-custom analog or RF layout for high performance chips
• Proven track record where products have gone to volume production a plus

• Bachelor’s degree in Electrical Engineering or other technical field
• 10+ years in full-custom analog or RF layout for high performance chips
• Experience maintaining EAD tools for DRC, LVS, RC extraction, and design database management.
• Experience writing or modifying DRC rules files; a plus
• Strong written and verbal skills