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Intel NOC Lead Design Engineer Malaysia, Penang 298506634
In Q4 2023, Intel announced PSG will be reported as a separate business unit beginning on January 1, 2024 with ongoing support from Intel. This position is associated to that standalone business strategy and is expected to fully transition to a standalone company at some time in the future.
Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design.
Participates in the definition of architecture and microarchitecture features of the block being designed.
Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence.
Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Follows secure development practices to address the security threat model and security objects within the design.
Works with IP providers to integrate and validate IPs at the SoC level.
Drives quality assurance compliance for smooth IPSoC handoff.
Qualifications
Bachelors degree in Electrical/Computer Engineering or related field and 7+ years of experience Or a Masters degree in Electrical/Computer Engineering or related field and 6+ years of experience.
5+ years of RTL coding and/or IP integration experience using Verilog/SystemVerilog.
2+ years prior experience in addressing LINT, CDC and Static Timing Analysis issues.
2+ years prior experience with Power UPF.
1+ years prior experience as IP design engineer or SOC integration engineer interfacing with IP design teams.
1+ year prior experience in SOC micro-architecture (clocking, reset, power, etc) in terms block diagrams, data flow diagram, algorithm state machine, finite state machines, and detailed timing charts.
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