Amazon DFT Design Engineer AWS Machine Learning Acceleration 

United States, Texas, Austin 

288321951

As a member of the Silicon Optimization Engineering Team you’ll be responsible for the design and optimization of hardware in our data centers. You’ll provide leadership in the application of new technologies to large scale server deployments in a continuous effort to deliver a world-class customer experience. This is a fast-paced, intellectually challenging position, and you’ll work with thought leaders in multiple technology areas. You’ll have relentlessly high standards for yourself and everyone you work with, and you’ll be constantly looking for ways to improve your products performance, quality and cost. We’re changing an industry, and we want individuals who are ready for this challenge and want to reach beyond what is possible today.Key job responsibilities
• Develop, implement and verify state-of-the-art Design for Test (DFT) architectures
• Work with block designers to integrate DFT implementations
• Work with physical design team to setup and implement DFT insertion flow
• Develop high coverage and cost effective DFT methodologies
• Perform RTL coding and Verification
• Participate in Silicon debug and write scripts to effectively handle ATE related data
• Communicate and work with team members across multiple disciplinesA day in the life
About the teamDiverse Experiences
AWS values diverse experiences. Even if you do not meet all of the qualifications and skills listed in the job description, we encourage candidates to apply. If your career is just starting, hasn’t followed a traditional path, or includes alternative experiences, don’t let it stop you from applying.
About AWSInclusive Team CultureWork/Life BalanceMentorship & Career Growth
We’re continuously raising our performance bar as we strive to become Earth’s Best Employer. That’s why you’ll find endless knowledge-sharing, mentorship and other career-advancing resources here to help you develop into a better-rounded professional.

- BS degree in EE, CE, or CS
- 3+ years of practical DFT experience with large processor and/or SoC designs
- Knowledge about industry standard tools and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time
- Experience with automation script development

- MS degree in EE, CE or CS
- Good breadth of knowledge in chip design from micro-architecture through physical design
- Good knowledge of design verification (DV) simulation methodologies
- Experience with large gate-level simulation setup and debug with SDF
- Strong programming and scripting skills in Perl, Python or Tcl
- Experience with industry standard DFT/SCAN/ATPG tools
- Experience with STA constraints development and analysis for DFT modes
- Practical experience with silicon debug