In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to the following:Develop detailed test and coverage plans based on the micro-architecture. Develop verification methodology suitable for the IP, ensuring scalable and portable environment. Develop verification plans for all features under your care. Implement verification plans, including design bring-up, DV environment bring-up, regression enabling for all features under your care, debug of the test failures. Develop block, IP and SoC level test-benches.