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Apple Cellular PPAC Power Performance Area Cost Engineer United States, West Virginia 280441145
05.09.2025
In this highly visible position as a key technical member of the Cellular Power Performance Area & Cost optimization team, you'll play a crucial role in improving the Power, Performance, Area, and Cost efficiency metrics of Apple Cellular silicon. Your responsibilities will include optimizing Design and Implementation methodologies for cellular chips to achieve best-in-class efficiency metrics across all PPA dimensions. You'll identify and drive improvement opportunities through custom/semi-custom flows, IP development, design technology co-optimization, and advanced analytics. With practical design knowledge, you'll help differentiate and streamline Apple's silicon engineering methods.
As a PPAC Optimization Engineer, you'll optimize the design and implementation methodology for cellular chips across multiple focus areas including area efficiency, power optimization, and design technology co-optimization. Your primary responsibilities will involve optimizing Power, Performance, Area, and Cost efficiency metrics through various approaches:- Identify utilization bottlenecks in physical design and develop architectural, design, and implementation-level solutions to improve utilizations.- Develop and implement Vmin and power optimization methodologies- Perform design technology co-optimization analysis, including optimal voltage point analysis for performance/power curves and identification of scaling trends and bottlenecks in new technology nodes- Conduct in-depth analysis of Frontend and Backend databases, as well as post-silicon data, to identify critical issues and improve PPA
- Minimum BS and 10+ years of relevant industry experience.
- VLSI background with hands-on experience in RTL to GDSII flows.
- Prior experience in doing Power, Performance, Area and Cost optimizations for SoCs.
- Experience with SoC power flows & Vmin optimization.
- Experience with Design Technology Co-optimization, identifying and solving scaling bottlenecks in new technology nodes.
- Rapid prototyping and scripting of methodologies and test chip block implementation.
- Solid understanding of Physical Design challenges, proficiency with synthesis, place and route tools, and implementation exploration.
- Experience with Metal stack optimizations.
- Experience performing Early Tech node analysis to identify implementation bottlenecks.
- Design Technology Co-optimization expertise.
- Strong analytical skills and ability to identify and communicate high return on investment opportunities.
- Ability to apply data science and ML analytics for Frontend and Backend databases, as well as post-silicon data, to identify trends & patterns and fine-tune implementation methodologies.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
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