Intel Layout Design Engineer Mexico, Jalisco, Guadalajara 277426321
Designs and optimizes custom physical layouts for analog, mixed-signal, and memory circuits in CMOS technology, ensuring performance, area, and reliability goals are met.
Your responsibilities will include but not limited to:
- Plan, design, and validate highly customized physical layouts using Virtuoso XL.
- Collaborate with circuit designers to meet functional and performance specs.
- Leverage best-known methods to create high-quality layouts efficiently.
The ideal candidate should exhibit the following behavioral traits:
- Advanced problem-solving skills, collaboration, and team skills.
- Advanced English communication skills.
Minimum qualificationsare required to be initially considered for this position.
- Bachelor's degree in electrical engineering or related field.
6+ months of experience working with any of the following
- EDA tools, DRC/LVS, and CMOS process.
- Design hierarchy, hierarchical layout integration, using fill to meet design rules in a block, and layout floorplan.
- Basic integrated circuit operation.
- Unix environment.
Must have unrestricted - permanent right to work in Mexico.
The position is in Mexico; it is not eligible for employment-based visa/immigration sponsorship.
Preferred qualificationsare in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
2+ years of experience working with:
- Device-level CMOS analog/memory custom layout design. Experience with advanced process nodes.
- ICC, Fusion compilers, and ICWBEV+
- Scripting skills (Python, SKILL) for automation.
- Berkely Analog Generator.
- Knowledge of VLSI design.
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orschoolwork/classes/research.
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