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NVIDIA is hiring a SOC/IP Methodology Engineer to help design and architect next generation custom SoC/IP solutions. We are looking for special individuals with passion and desire to deliver innovative products. Together, we will build the next generation of life changing SoC’s. If you are a motivated individual that understands how SoC systems are architected and built, has intimate knowledge of client requirements, and understand various development cycles, this is your place to be.
What you will be doing:
Responsible for developing and optimizing semi-custom design methodologies, work with internal and external collaborators and IP Vendors on SOC/IP requirements and drive technology alignments across them.
You will be a hands-on domain professional, able to traverse from RTL to final design closure (timing and layout) involving latest EDA technologies and capabilities.
Identify inefficiencies and improvement opportunities in the front-end chip implementation process and propose ideas to address them
Own front-end design quality checks and reviews to present the physical design team with high-quality RTL
What we need to see:
BS/MS in Computer or Electrical Engineering or equivalent experience
Proven ability in chip design, with 5+ years of specializing in SOC integration and design automation
Excellent analytical and problem-solving skills
Experience in RTL design (Verilog), verification (UVM, System Verilog), System-On-Chip design/integration flow, and design automation
Strong coding skills in Perl, Python, or other industry-standard scripting languages
Hands-on experience with physical design and analysis tools from EDA vendors such as Cadence, Synopsys, Mentor (CDC, LP Checks, Genus, First Encounter, Innovus, Design Compiler, Fusion Compiler) etc.
Experience with integrating MBIST/DFT is a plus
You will also be eligible for equity and .
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