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Apple IP Design Verification Engineer United States, West Virginia 261430608
09.09.2025
This role is for a Design Verification Engineer who will enable us to produce fully functional first silicon IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.
In this role, you will be responsible for ensuring bug-free first silicon for part of the IP and are expected to: Develop detailed test and coverage plans based on the micro-architecture Develop verification methodology suitable for the IP, ensuring a scalable and portable environment. Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage and more.
- 7+ years’ experience in digital logic design verification.
- Basic knowledge of SystemVerilog and UVM.
- Experience developing UVM based IP test-benches
- Experience with complex designs and advanced debug skills ability
- Experience with verification tools such as simulators, waveform viewers, build/run automation, coverage collection and analysis, gate level simulations
- Strong communication skills are a must, as the candidate will interface with a lot of different groups within the company.
- Ability to work well in a team and be productive under tight schedules
- PREFERRED
- Excellent knowledge of one of the scripting languages: Python, Perl, TCL
- Experience with serial/parallel protocols such as PCIe or DRAM
- Proven knowledge of formal verification methodology
- In lieu of UVM knowledge, C/C++ experienced level knowledge
- Experience with Lab hands-on debug
- 7+ years’ experience in digital logic design verification
- BS.c or MS.c in Electrical Engineering
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