Researching and crafting architecture solutions for chip-to-chip communication, optimizing for performance, area, power, security, and resiliency
Working with other design teams to define interfaces and flows between NVLink C2C blocks and the rest of the chip
Architectural modeling, validation, definition and documentation
Driving implementation across design, verification, firmware and software teams
Working with various teams to define NVLink C2C architecture
MS or PhD in Electrical Engineering, Computer Science or Computer Engineering (or equivalent experience)
At least 10+ years of relevant experience in some combination of architecture, design, and verification
Proven experience over link layer architecture (Transaction layer, Data link layer, Physical layer)
Experience with existing interconnects (PCIE, UCIE, Chip to Chip links)
Able to define system architecture with NVLINK-C2C interconnects and SW stack around it
Knowledge of Industry standard protocols CHI/CXL/AXI
Collaborate with multi-functional teams including IP, SoC, physical/package design, firmware, electrical design, and validation to drive interconnect technology development and integration
Evaluate and trade off technical solutions to meet platform requirements for current and future products
Lead projects from concept through product lifecycle, including pathfinding, prototyping, and deployment
Have completed and shipped multiple projects and are skilled at I/O Architecture.
You will also be eligible for equity and .
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