Microsoft Senior Validation Engineer 

United States, California, Mountain View 

249053839

Senior Validation Engineerto work in the dynamic Microsoft Artificial Intelligence System on Chip (AISOC) Silicon team. You will be part of the Post-Silicon Validation team, driving many facets of high performance, high bandwidth designs.

Required Qualifications:

• 7+ years of related technical engineering experience
  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience
  • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.

• 6+ years of experience in pre-silicon and post-silicon validation with a proven track record of delivering high performance Central Processing Unit (CPU), Vector processors and Graphics Processing Unit (GPU’s) or relevant experience.

Other Requirements:

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred Qualifications:

• Applied understanding of Computer Architecture and System on Chi(SoC) validation principles, including:
  • Broad understanding of SoC subsystem, SoC system level, and platform level functionality.
• Writing scripts/software with industry standard languages such as Python or C/C++. Experience in Matlab a plus.
• Hands-on experience with electrical compliance test on latest Ethernet, PCIe and other SerDes interfaces involving both Non Return To Zero(NRZ) and Pulse Amplitude Modulation with 4 levels(PAM4). Experience with relevant test equipment such as Bit Error Ratio Test(BERT) Scopes, traffic generators and protocol analyzers.
• Hands-on experience with debugging complex Electrical and Signal-Integrity issues for high speed serdes.
• Worked on fully characterizing Serdes interfaces and generating compliance reports.
• Experience in training links, and optimizing settings to get robust channel performance.
• Understanding of Ethernet standards.
• Developed characterization automation software, incorporating required characterization equipment and fixtures.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

Microsoft will accept applications for the role until July 18, 2024.

• Develop validation strategy, test plans and Bring-up, Validate and Characterize high speed Ethernet and Peripheral Component Interconnect Express(PCIe) interfaces. Run protocol specific compliance tests.
• Execute content in post-silicon, triage, and debug failures.
• Apply your growth mindset to learn and adapt in a complex and dynamic environment.
• Engage with partners to drive continuous improvement to design, validation plans/collateral, and methodology to prevent, reduce, and/or find bugs sooner, more easily, or more reliably.
• Provide technical guidance, coaching, and mentorship to other engineers.
• Collaborate with and influence architects, logic designers, verification engineers, other post-silicon validators, and IP and tool providers.
• Provide technical leadership with respect and integrity.
• Apply your experience towards pre-silicon verification plans, tests, and debug of your area.
• Other
  • Embody our and