Nvidia Senior IC Failure Analysis Engineer 

Israel, North District 

24141009

NVIDIA Networking IC Product Engineering team is looking for an IC failure analysis engineer to support failure analysis activities for yield improvement, product bring-up, customer returns, and product qualification. As a failure analysis engineer, you will own the physical failure analysis (PFA) part, develop workprocedures/techniques/recipes,and perform PFA of IC’s using in-house equipment and in external labs. In addition, you will be responsible for all the mechanical aspects of the electrical failure analysis (EFA): sample preparation, mechanical setup, device cooling, and additional challenges to enable debug techniques such as LADA, Emission, OBIRCH, and laser probing.

What you will be doing:

• Perform hands-on die level and package level PFA using in-house equipment and equipment available in external labs

• Manage tasks in external labs

• Work closely with the EFA engineers and mechanical engineers to find solutions to enable EFA of IC’s and consistently learn and improve them

• Develop our sample preparation techniques and approaches for EFA

• Document work procedures and writing PFA reports

What we need to see:

• BSc in Materials/chemical engineering, chemistry, physics, or related fields

• 4+ years of hands-on experience in PFA, metallography, materials testing lab, or similar

• Ability to work and collaborate as part of a team and independently

• Self-motivated with the ability to learn alone and review the literature to find solutions to our challenges. On the one hand, collaborate and understand the team and customers’ needs, and on the other hand, develop the best solutions

• Insist on high standards for high-quality samples

• Good documentation and communication skills

Ways to stand out from the crowd:

• Good understanding of VLSI circuit design, and/or device physics, and/or process engineering

• Previous experience in mechanical cross-sectioning of PCBA or IC package

• Previous experience in different methods of IC delayer

• Experience with SEM or FIB for cross-sections and preparing lamella for TEM

• Experience in data analysis (JMP or similar)