Nvidia ASIC TOP Floorplan Intern - 

China, Shanghai 

221548429

What you will be doing:

• Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development.

• Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities.

• Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions.

• You will build tools and improve existing infrastructure to optimize chip area and speed of execution.

What we need to see:

• Pursuing Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering.

• Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure.

• Strong communication and interpersonal skills and ability & desire to work as a great teammate should be displayed in your interview.

• Python, Perl and C/C++ programming language experience.

Ways to stand out from the crowd:

• Excellent speaking English is a big plus score.