Nvidia ASIC Physical Design Intern 

China, Shanghai 

675057324

What you'll be doing:

• Chip integration and netlist generation, cross-team collaboration to implement chip partitioning and floorplan

• Synthesis, RTL/netlist quality check, formal verification, function eco creation

• Constraints creation and validation, timing budget, work with ASIC team to analyze/resolve function timing issues, achieve all special timing closure, such as io, test, clock, async etc.

• Work in conjunction with PR engineers for chip implementation to achieve full chip timing closue

• Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout), flow automation development for above areas

• Methodology in any of above areas.

What we need to see:

• Currently pursuing a Master's or PhD degree within a relevant or related field

• Strong knowledge in IC design

• Passionate about technology research and IC backend

• Self-driven, good leaning ability, good teamwork

• Excellent communication skill, proficient in English reading and writing

Ways to stand out from the crowd:

• Experience in IC backend implementation

• Hand-on experience in EDA software from Synopsys (DC/PT/Formality), Cadence (RC compiler/LEC)

• Proficient user of Python or TCL