Cisco ASIC Package Mechanical Engineering Technical Leader 

Taiwan, Taipei, Taipei 

219722171

• Perform finite element analysis to evaluate thermal mechanical stress, warpage, solder joint reliability of ASIC package, substrates, and advanced packaging assemblies
• Simulate and analyze linear/nonlinear material behaviors, such as plasticity, creep, and viscoelasticity, relevant to solder joints, Copper, stiffener, and underfills
• Develop and automate simulation workflows using Python, Fortran or similar scripting tools to streamline analysis and reporting
• Provide clear simulation results to support mechanical design, root cause analysis, and risk mitigation
• Support design optimization at early phase of product development and failure investigations by correlating FEA predictions with test data and field returns
• Document and present analysis results, assumptions, and design recommendations in a clear, structured format

Minimum Qualifications

• Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience
• At least 3 years of experience in mechanical design and thermomechanical simulation of semiconductor packages
• Hands-on experience with 3D modeling, finite element analysis using ABAQUS or ANSYS
• Flexibility to coordinate and communicate across different time zones, supporting global project teams in the US and Asia

Preferred Qualifications

• 5+ years of experience in mechanical or thermomechanical simulation of semiconductors or electronics packaging systems
• Knowledge of GD&T, design-for-reliability (DfR) principles and industry standards (JEDEC, IPC, etc.)
• Experience in flip chips, 2.5D/3D advanced packaging, and/or heterogeneous integration technologies
• Familiarity with material mechanical behavior and material characterization and working knowledge of reliability qualification of semiconductor packages
• Proficiency in script-based automation for simulation to improve simulation efficiency and consistency