Intel Full Chip Layout - Physical Architect 

United States, Texas 

219657595

Responsibilities will include but are not limited to:

• Defines the physical dimensions of the IP or SoC with consideration for overall product costs such as die size optimization,dieperreticle/gooddieperwafer
• Establishes the integration plans for disaggregated die with optimization for package and board constraints.
• Performs integration of all dies in a package and completes the relevant checks before tape out.
• Creates and physical database for the IP or SoC.
• Collaborates with architects to optimize the placement of IPs for latency as well as die area/aspect ratio.
• Creates specifications and collaterals for the IP blocks to execute the floorplan and automatic place and route (APR) at subsequent hierarchies.
• Collaborates with the clock design and logic design teams to deliver the physical block level floorplans for APR.
• Collaborates with the power delivery team on tradeoffs for metal allocation for signal and power.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

The candidate must have at least one of the following:

• Bachelor's Degree in Computer/Electrical Engineering or Computer Science with 9+ years of experience.
• OR Master's Degree in Computer/Electrical Engineering or Computer Science with 6+ years of experience.
• OR PhD in Computer/Electrical Engineering or Computer Science with 4+ years of experience.

Experience listed above must be in the following:

- Experience owning the full chip level and taping out multiple complex SoCs.

- Experience in floor planning, Synthesis, Clocking, Timing Analysis, Place, and route.

Preferred Qualifications:

• Leading the project from all the technical aspects right from Synthesis to Tape-out
• Supporting the team members in closing any design issues.
• Hands-on experience with industry standard Cadence or Synopsys tool suite, and other Sign-off tools from Siemens(Mentor), Ansys etc.
• Good understanding of Full-Chip Level Partitioning, Floorplanning, PnR, CTS, different clocking techniques for skew and delay balancing, multiple clock complexity, time budgeting, timing closure techniques, PnR congestion analysis, resolving floorplanning issues, UPF (Low power design techniques), resolving formal verification, layout physical problems, understanding and hand-on experience of digital design sign-off tools like and not limited to noise analysis, layout closure, timing and functional eco closure, IR drop analysis etc.
• In-depth understanding on rtl to gds2 flow and understanding of basic device physics.
• Past experience with internal flow development and understand nuances of Physical Design (Structural Design) flow.
• Minimum 2+ years experience with technically leading junior (fresh out of school) to senior/experienced individual contributors
• Experience with handling developing PDKs (Process Design Kit)
• Working experience with cutting edge technology (5nm or below)
• Very good handle on Tape-out interaction with the foundry and worked on Post-Silicon activities.
• Scripting proficiency in PERL, tcl
• Own any technical task in SoC physical Design work.
• Documented experience in technically leading past SoC full chip level physical design execution
• Exposure to various industry standard Physical Design and Sign-Off closure tools.
• Understanding of peer domains to Physical Design, viz., RTL, verification, DFx, post-Si etc.
• Exposure to various industry standard Physical Design and SIgn-Off closure tools

Experienced HireShift 1 (United States of America)US, California, Santa ClaraUS, Oregon, Hillsboro, US, Texas, Austin
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

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