As a memory sub-system verification engineer, you will have the responsibilities as follows:- Play a meaningful role in end-to-end verification of memory subsystem by developing an in-depth understanding of cache coherence protocols and functioning of various units in CPU/GPU/SOC that are relevant to memory subsystem verification. These units include Load-Store unit, different levels of caches, bus interface units, memory controller, etc. - Develop verification environment which can be used in both simulation and emulation- Develop synthesizable transactors and test benches and support verification hooks for verifying memory subsystem functionality and CPU/SOC features - Develop unit level stimulus as well as full chip assembly programs to verify memory subsystem- Work closely with CPU/SOC/GPU RTL design teams and understand the specification in detail for developing verification strategy for the above mentioned environment taking system level considerations into account. - Develop coverage monitors and accomplish coverage goals- Debug failures in both pre and post silicon environments, root-cause problems, and propose design changes to address issues- Develop abstract end-to-end checks to verify CPU-SOC memory subsystem interaction and coherence protocols. - Use novel techniques such as formal verification, emulation/FPGA technology, as well as industry standard tools and languages to verify memory subsystem