Intel GPU Logic Design Engineer 

United States, Texas 

200515454

Job Description:

As a Graphics IP Design Engineer, you will be responsible for developing and optimizing the logic design and register transfer level (RTL) coding for graphics IPs, including graphics, compute, display, and media. Your key responsibilities will include:

• Design and Development:
  • Develop logic design, RTL coding, and simulation for graphics IPs to generate cell libraries, functional units, and the GPU IP block for integration into full chip designs.
  • Participate in defining architecture and microarchitecture features of the block being designed.
• Optimization and Implementation:
  • Apply strategies, tools, and methods to write RTL and optimize logic, ensuring the design meets power, performance, area, and timing goals, as well as design integrity for physical implementation.
• Verification and Quality Assurance:
  • Review verification plans and implementations to ensure design features are correctly verified across verification hierarchies.
  • Drive unit-level verification and resolve failing RTL tests, implementing corrective measures to ensure feature correctness.
• Customer Support:
  • Support SoC customers to ensure high-quality integration of the GPU block.

The ideal candidate should demonstrate:

• Ability to clearly articulate ideas and technical concepts to both technical and non-technical stakeholders.
• Proven experience working effectively in a team setting, contributing to group goals, and supporting colleagues.
• Strong analytical skills and creativity in approaching complex challenges and developing innovative solutions. Flexibility in adjusting to changing priorities, technologies, and project requirements.
• Skill in managing multiple tasks and projects efficiently, meeting deadlines, and prioritizing effectively.
• Ability to evaluate situations, make informed decisions, and anticipate potential issues.

Minimum Qualifications:To be initially considered for this position, candidates must possess:

• Education and Experience:
  • Bachelor's Degree in Electrical/Computer Engineering, Computer Science, or a related STEM field with 5+ years of experience. OR
  • Master's Degree in Electrical/Computer Engineering, Computer Science, or a related STEM field with 2+ years of experience.

• Relevant experience in:
  • RTL design and optimization to meet power, performance, area, and timing goals, ensuring design integrity for physical implementation.
  • System Verilog and UVM.
  • Python or similar scripting languages.

Preferred Qualifications:In addition to the minimum requirements, the following qualifications are considered a plus factor in identifying top candidates:

Experience with RTL design and optimization for power, performance, area, and timing goals, ensuring design integrity for physical implementation.

Exposure to CPU or GPU Architecture and Computer Architecture Knowledge.

Debug experience with industry-standard frontend design and verification flows, tools, and methodologies.

Experienced HireShift 1 (United States of America)US, Arizona, PhoenixUS, California, Folsom, US, California, Santa Clara

Benefits:

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.