Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
5 years of experience with verification methodologies and languages such as UVM and SystemVerilog.
Experience developing and maintaining verification test benches, test cases, and test environments.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
Experience in different verification techniques and methodologies including formal, Gate-Level Simulation, Unified Power Format based Power simulations, UVM and C based testing, to achieve bug-free Silicon in SoCs.
Experience in Advanced RISC Machine (ARM) and RISC-V processor based Design Verification including tool chains and C based testing.
Experience in low-power design verification.
Experience with Interconnect Protocols (e.g. AXI, APB, ACE).