Qualcomm NoC Interconnect Design Engineer Architect 

United States, California 

199044200

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

The NoC bus team group consists of a multi-disciplinary group involved from early product specification and analysis effort to final RTL delivery to the SoCs. One aspect of the process is to identify architecture bottlenecks and drive micro-architecture choices using performance and power analysis, and to provide the SoC team with design guidelines for bus protocol compliance and best power interconnect.

Responsibilities:

The successful applicant will be responsible for creating micro-architecture bus components specifications as well as analyzing the performance results, deliver RTL and run tool flows. Responsibilities also include evaluating new IPs, driving new protocol deployments as well as defining system wide guidelines for IPs to inter-operate together in the SoC. Candidate should also be able to deliver RTL to the SoC team, support verification and silicon validation teams, and work with SW teams to support successful deployments of the interconnects.

Skills/Experience:

• Knowledge of various bus protocols (AHB, AXI, CHI, …), network on chip.

• Familiarity with ARM GIC architecture and interrupt routing mechanisms.

• Strong working knowledge of architecture tradeoff analysis and performance trouble shooting.

• Strong knowledge of ASIC flow (synthesis, STA, Lint), power tools.

• Ability to define bus components micro-architecture while taking into account performance/power/area tradeoff.

• Ability to quickly react and adapt to changes.

• Excellent communication skills.

• Familiarity with CPU architecture is a big plus.

*All levels including New College Grads, welcomed to apply- Salary range varies depends on experience level

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.

PhD in Science, Engineering, or related field.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

Pay range:

$108,000.00 - $177,500.00