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Apple PLL/Clocking Design Engineer United States, Texas, Austin 19490173
31.03.2025
- BSEE required or years of relevant experience. MSEE preferred
- Technical Expertise: Demonstrated proficiency in PLL/FLL and frequency synthesis architecture and circuit design. This includes digital and analog approaches, DCO/VCO design both RO and LC, Fractional-N, SSC, Spur and Jitter cancellation techniques ..etc
- Good knowledge of band gaps, bias circuits, op-amps, LDOs, feedback and compensation techniques.
- Clocking Mastery: Deep understanding of clocking fundamentals, with a solid grasp of phase noise, jitter analysis, budgeting, and feedback loop dynamics.
- Simulation and Modeling: Skilled in developing System Verilog models, and performing behavioral simulations to explore new architectural performance and impact on loop dynamics. Ability to design/debug RTL is a plus.
- Attention to Detail: Exceptional focus on understanding the problems at hand and their systemic impacts, ensuring thoroughness in problem-solving.
- Innovation and Learning: A history of innovation and self-directed learning, with demonstrated leadership skills and a growth mindset.
- Team Collaboration: Outstanding teamwork capabilities paired with strong productivity and scripting skills, ideally with experience in using industry-standard design tools.
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