Job Description:
Job Description:
Layout design of digital high-performance blocks
Timing closure of the blocks with best PPA(power/performance/area)
Ideal Candidate Will Have:
Strong understanding of physical implementation.
Experience working with advanced semiconductor technologies.
Experience in implementing low power and high-performance cores
Excellent communication and cross-functional collaboration skills.
Ability to analyze complex trade-offs and make data-driven decisions.
Master’s degree with 6+ years or PhD with 3+ years of hands-on experience with Place and route tools; PhD in Engineering is a plus
Compensation and Benefits
The annual base salary range for this position is $120,000 - $192,000
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
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