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What you'll be doing:
Focus on IP verification at full chip/system-level of ASIC design, architecture, golden models, and micro-architecture using advanced verification methodologies such as portable stimulus and UVM.
Develop verification test plans using portable stimulus to be implemented in simulation, C-model, emulation, and silicon environments.
Collaborate with architects, designers, and verification teams to achieve objectives.
Support software development and debug efforts both pre- and post-silicon.
Understand high-level system features of the design and their application across various platforms.
What we need to see:
A Bachelors or Masters Degree (or equivalent experience) in Electrical Engineering or Computer Science
2-4+ years of meaningful ASIC verification, Firmware Development, or System Level Diagnostics experience
Verification test planning, test bench architecture, problem solving and debug.
High level of working knowledge of Scripting Languages (Python, Perl)
Experience with System Verilog, SystemC/C++
Exposure to design and verification tools (VCS or similar simulation tools, debug tools like Debussy).
Understanding of Computer System Architecture
Strong interpersonal and remote collaboration skills and the desire to work as a phenomenal teammate are huge plus.
Ways to stand out from the crowd:
Experience with full chip or system level verification is highly desirable
Familiarity with portable stimulus methodology
Background with functional coverage and assertion-based verification methodologies
You will also be eligible for equity and .
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