Intel Senior DFT engineer 

India, Karnataka, Bengaluru 

171310588

Job Description:

As a member of the GHI DFT group, you will be responsible for one or more of the following activities:

• You will work on the design, RTL/GLS validation, automation, and/or timing analysis for Scan/ATPG and/or DFT/JTAG controller
• You will also contribute or be involved with trace/pattern generation efforts as well as post-silicon enabling, debug support, and/or analysis of the DFx features/content types you are responsible for.
• Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs.
• Participates in the definition of architecture and microarchitecture features of the block being designed.
• Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
• Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
• Supports SoC customers to ensure high-quality integration of the GPU block.

Qualifications:

The ideal candidate will exhibit the following traits/skills:

• Excellent written and verbal communication skills
• Demonstrate Leadership ability in driving execution
• Demonstrate teamwork, problem solving and influencing skills
• Ability to work with different geographical locations

Minimum Qualifications:

• Bachelors in Electrical/Computer Engineering or related field with 9+ years of experience. Or a Masters in the same fields with 7+ Years of academic or industry experience.
• Your experience should be in following
  • At least one of the key DFT features such as TAP/JTAG, Scan/ATPG or Array DFT (MBIST/PBIST) (This is a key skill requirement.)
  • SoC or IP DFT design, integration or verification
  • EDA tools such as ATPG tools, Siemens Tessent shell, VCS simulation and/or debug tools.

Preferred Qualifications:

• Silicon enabling debug or test pattern development experience
• Design automation skills and proficiency in programming or scripting languages
• Structural design flows, including timing, routing, placement or clocking analysis
• High volume manufacturing requirements and test flows
• 3D, media and display graphics pipelines
• SoC architecture

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