Amazon Senior DFT Engineer 

India, Karnataka 

705130203

Work hard. Have fun. Make history.We are seeking a seasoned and strategic Sr DFT Engineer to Lead end-to-end Design-for-Test (DFT) planning, execution, and silicon readiness for complex SoCs. This role demands deep technical expertise, hands-on ownership, and proven leadership in taking chips from design to volume production.As a Senior DFT Engineer, you will be both the technical owner and hands-on driver of the DFT strategy and execution across complex, high-performance SoCs. This role requires deep technical expertise, the ability to architect scalable and robust DFT solutions, and the discipline to personally engage in implementation and debug. You will work alongside world-class design, validation, and test teams to ensure first-pass silicon success and scalable production test readiness. Ideal for a seasoned leader, this role combines strategic ownership with direct execution, driving full lifecycle accountability — from early DFT architecture planning to high-volume silicon bring-up and yield ramp.Key job responsibilities
Key job responsibilities
 Lead development & implementation of DFT architecture including system level DFT for a full chip
 Write and guide others in writing design flow and project documentation.
 Own DFT planning, milestone tracking, and cross-functional checklist reviews.
 Oversee design, insertion, and verification of DFT logic and components into full SoC and subsystem RTL netlists.
 Review and sign-off SoC level DFT mode timing closure using static timing analysis
 Drive the sign-off on a generation of high-quality test and debug patterns for high coverage on silicon
 Keep informed on and introduce new technology into Design-for-Test process as appropriate.

Education:
BS/BE or MS/ME in Electrical Engineering, Computer Engineering, or related field.Experience:
 15+ years in SoC/ASIC DFT, including 3+ years Leading DFT.
 Proven DFT experience leading multiple SoCs/ASICs (end-to-end) from architecture to high-volume production.DFT Architecture Expertise:
Proven capability in architecting and implementing DFT strategies at both subsystem and top-level, including:
 Scan architecture, compression, and ATPG implementation for high fault coverage and test quality.
 MBIST, BISR, and BIHR flows, including advanced shared-bus memory BIST integration.
 IEEE 1149.x (Boundary Scan), IEEE 1500, and IEEE 1687 (IJTAG) test architectures.
 DFT-Aware STA closure, including constraint generation and timing convergence strategies for shift and capture paths.
 RTL and gate-level debug, including mismatch triage and simulation correlation.
 Insertion and Validation of EFUSE & OTP controllers and related structures during DFT implementation.Tool Proficiency:
Deep hands-on experience with Tessent / Industry Std EDA tools, including:
 IJTAG ICL extraction and PDL modeling.
 DFT logic insertion, pattern generation, and diagnostics.Design Background:
 Experience in writing verilog/system verilog RTL related to DFT logic design.Silicon Debug:
 Drive post-silicon validation, failure triage, and yield learning using SCAN diagnosis and MBIST repair signature analysis.Automation Skills:
 Ability to build and maintain scalable DFT automation flows using Python, Tcl, or Perl.
Execution Excellence:
 Known for being proactive, detail-oriented, and independently accountable for tapeout and post-silicon success.