Intel SOC Physical Design Engineer 

United States, California 

166189119

As a SOC Physical Design Engineer in NEX, you will

• Perform physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.
• Conduct all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
• Conduct verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
• Analyze results and makes recommendations to fix violations for current and future product architecture.
• Utilize expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.
• Optimize design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.

Responsibilities will include but not limited to:

• In this visible role, you will oversee the SOC physical implementation of a highly complex networking chip using cutting-edge technology nodes.
• Drive the execution of SoC design Physical design activities from synthesis to all the way to signoff.
• Work closely with the architect, RTL, and DFT teams to optimize/converge designs for better PPA.
• Channel analysis, feedthrough insertion, repeater/flop planning, custom route planning, and timing closure.
• Analysis of multiple power domains using standard power formats (UPF or CPF).

What we need to see (Minimum Qualifications):

• Candidate must have a bachelor's degree in EE/CE/CS with 8+ years OR Master's degree in Computer science/Electrical or Computer Engineering with 6+ years of experience in:
• 5 + years’ experience with Physical design/integration execution of complex SOCs/ASICs in 5nm and below.
• 5 + years’ experience with microelectronic designs, semiconductor device physics, the CMOS process, and physical layout.
• 5 + years’ experience in tools such as Design Compiler, ICC2/Innovus, Primetime, etc.
• 4+ years’ experience of DFT, DFM, clocking, FEV, top-down and bottom-up design flows.
• 4+ years’ experience scripting in PERL, TCL.

How to Stand Out (Preferred Qualifications):

• Experience working with advanced process nodes such as 5nm and below
• Expert in physical design tools such as Design Compiler, Fusion Compiler, and Conformal.
• Experience in full-chip Formal verification, signal EM, IR-drop analysis, STA, and physical verification.
• Knowledge of floor planning, pin placement, and SOC integration.
• Experience with various types of external interfaces, such as DDR, PCIe, and similar
• Experience as a team lead.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing BenefitsAnnual Salary Range for jobs which could be performed in US, California: $162,041.00-$259,425.00
*Salary range dependent on a number of factors including location and experience