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Apple Power UPF Methodology Engineer United States, Texas, Austin 161456288
16.02.2025
Description
You will have the opportunity to integrate and come-up with new insights, as well as work with a team of hardworking engineers. The main responsibility of this role is to develop and support transistor level power ERC sign-off for digital and mixed signal designs, drive power ERC sign-off at full-chip level, drive UPF implementation and verification for mobile SOCs and make current power sign-off flow more robust and expand power sign-off methodology for next generation mobile products, including:
Minimum Qualifications
- BS and a minimum of 3 years of relevant industry experience
Preferred Qualifications
- We are looking for applicants with experience in ASIC design methodology and an emphasis on power definition.
- Experience in ASIC design flows and custom IP design flows.
- Familiar with basic circuit & layout fundamentals.
- Familiar with Caliber based ERC flows.
- Familiar with power intent definition, implementation and verification flows.
- Knowledge of scripting languages like, Tcl, Perl and Python.
- Familiar with of power analysis and optimization methods.
- Familiar with entire RTL2GDS flow (RTL sim (VCS), equivalence, synthesis, P&R, intent checking)
- Strong communication skills are a pre-requisite as you will collaborate with a lot of different groups.
Additional Requirements
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
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