Intel SOC RTL Design Engineer Lead 

United States, California, San Jose 

152204841

the competition. These devicesheterogeneous 3D system-in-package technology along with the leading-edge process technologies which will ensure our continued market leadership. Altera is committed to aggressivelyour position for a broad range of market segments. Altera products haveuses covering industrial automation, space exploration, data centers, automotive, and internet routers to name a few.

Job Description:be responsible fordeveloping the logic design, register transfer level (RTL) coding, and simulation for SoC designs. This role involves integrating logic of IP blocks and subsystems into a full chip SoC or discretedesign.

Key responsibilities include:

• Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design

• Integrates logic of IP blocks and subsystems into a full chip SoC or discretecomponentdesign

• Participates in the definition of architecture and microarchitecture features of the block being designed

• Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence

• Applies various strategies, tools, and methods to write RTL andoptimizelogic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation

• Reviews the verification plan and implementation to ensure design features are verified correctly

• Resolves and implements corrective measures for failing RTL tests to ensure correctness of features

• Follows secure development practices to address the security threat model and security objects within the design

• Works with IP providers to integrate andvalidateIPs at the SoC level

• Drives quality assurance compliance for smooth IP/SoC handoff

• Excellent communication and documentation skills

• Mentoring team members

You must possessbelow minimum education requirementsand minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience.preferred qualifications are in addition to therequirements and are considered a plus factor in

Requirements:

• Bachelor's degreewith 9+years of experience,orMaster'sdegreewith6+ years of experience, orPhDwith 4+ years of experience ineitherElectrical or Computer Engineering, Computer Science, Math, Physics, orSTEM-related

• 9+ years of experience in RTL and System Verilog.

• In-depth experience withhardware design, including logic design, state machines, control units, processor sub-systems, and network on chips.

• In-depth knowledge of industry-standard tools and flows for front-end design, including synthesis, STA, Spyglass-based checks, and power domains.

Preferred Qualifications:

• Experience with AES/SHA, as well as compression and decompression algorithms

• Knowledge of Network on Chips and Control Processors

• Experience in programming languages such as Python