Marvell Senior Principal Verification Engineer 

United States, California 

147282739

What You Can Expect

• Embedded FW that runs on our RISC-V-based multi-core MCU, which controls our proprietary DSP data path

• C SDK provided to customers for interfacing and controlling our product

• Python-based GUI for in-field debug, status, and control

• Build, test, and automated regression infrastructure for the above

What We're Looking For

• Bachelors/Masters degree in CSE/ECE or related technical field(s)

• 7 to 18 years of experience in memory constrained embedded C/C++ FW development

• SW Team Lead or Technical Lead on embedded projects; project management & release planning, architecture design & development, code reviews & testing, through to customer volume production

• Understanding of embedded SoC, micro-controller architecture (RISC-V architecture a plus), memory-mapped hardware interfaces, GPIOs, ISRs, etc.

• Excellent verbal and written communication skills in English, and able to collaborate in a large cross functional organization

• Excellent problem-solving and customer debug skills on real hardware in the lab

• Experience with using revision control and defect tracking systems (git & Jira or similar)

Good to have the below skillset:

• Experience with SERDES, IM-DD/Coherent DSP, Ethernet/PCIe PHYs, and/or Optical Module SW

• Experience withdesigning/developing/debuggingsoftware state machines, transitions, context saving, error handling

• Experience with mixed-signal (analog+digital) control and monitoring, PID/feedback loop control, etc.

• Experience with bare-metal, RTOS, device driver, Linux kernel, etc.

• Familiarity with advanced compiler options and details (clang/gcc preferred)

• Proficient in C and Python, with knowledge of git, Linux, makefiles, gdb, IDEs, bash, etc.

• Familiarity with digital verification test flows, FPGA emulation, hardware languages such as Verilog

• Familiarity with lab equipment such as oscilloscopes, supplies, PNAs, ONTs, etc.

• Understanding of networking from the OSI model, with emphasis on the PHY up to the data link level

Understanding of signal processing: histograms, BER, SNR, sampling phase, Shannon limit, impulse & frequency response, FFT, etc.