דרושים Environmental Engineer – Industrial & Hazardous Waste Management ב-Samsung ב-ארהב

Role and Responsibilities

• Leads projects related to incoming technology transfer, production ramp up, new product introductions, yield improvement, stop loss reduction, cycle time reductions and other KPI improvements.
• Design, execute, and analyze experiments.
• Uses software to analyze data including statistical analysis; Consults with senior level engineers on experimental results in order to make decisions about large scale changes.
• Participate in Task Force Teams.
• Responsible for critical or complex steps or layers in the wafer fabrication process.
• Develops Change Point Management Plans.
• Communicates technical information to senior leadership outside of the department through presentations.
• Communicates Foundry Product’s technical summary to Foundry Customer
• Completes other duties as assigned.
• On-site work commitment. Location: Austin, TX.

Skills and Qualifications

• Bachelor’s degree in Physics, Chemistry, Electrical Engineering, Chemical Engineering, Materials Science or related field is required. Master's or Ph.D. is preferred.
• Prefer >2 years of work experience in the semiconductor industry with adequate knowledge on FINFET process integration, including thin films deposition, lithography, etch, diffusion, wet process, Cu plating, and / or CMP.
• Expertise in Excel, PowerPoint, and various statistics programs (JMP, Spotfire).
• Experience in med and high voltage development on any device node, design rule or PDK would be a plus.
• Experience in Python / R / SQL script coding for work efficiency enhancement would be a plus.

Note: This position is Full-Time onsite.

We offer a comprehensive benefits package, including:

• Medical, dental, and vision insurance
• Life insurance and 401(k) matching with immediate vesting
• Onsite café(s) and workout facilities
• Paid maternity and paternity leave
• Paid time off (PTO) + 2 personal holidays and 10 regular holidays
• Wellness incentives and MORE
  

All positions at SAS are full-time on-site.

This role requires access to information subject to U.S. export control laws. Applicants must be authorized to access such information or eligible for government authorization.

Role and Responsibilities

As a seasoned DFx engineer, you will be involved across the entire spectrum of activities all the way from defining the DFT scan architecture through implementation and culminating in pattern generation including silicon debug. You will be working on IP-level projects (GPU, system interconnect) in bleeding-edge processes that continually drive high test-coverage requirements.

• You understand SOC requirements and project milestones to help define a DFT architecture which optimally balances between coverage, test-time, andexecution.
• You create a detailed implementation spec which documents details of the architecture including SOC-level interface, clock design, and support of various test/debug modes.
• You close on the spec with stakeholders including DFX / RTL / SOC / STA / PD teams.
• You implement DFT scan: RTL creation, LINT, timing-constraints, ATPG andsimulation.Benchmark test-coverage and test-time to ensure that they meetexpectations.
• You drive towards continuing DFX excellence: improving test-coverage, minimizing test-time, and exploring tools / methods that improve execution efficiency.
• You build strong collaboration with SOC and Product/Test Engineering teams to quickly resolve any silicon issues including test-escapes and yield loss.

Skills and Qualifications

• 10+ years of experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 8+ years of experience with a Master’s degree, or 6+ years of experience with a PhD
• 10+ years of DFx expertise encompassing multiple tapeouts for digital IP (CPU / GPU) and/or SOC projects
• Demonstrated ability to architect DFT solutions from scratch on at least 1 project, and to create detailed specifications that can be used as a blueprint for implementation.
• Detailed understanding of test-coverage requirements across various scan modes especially as they pertain to bleeding-edge process nodes.
• Strong familiarity with RTL coding & STA with working knowledge of Physical Design
• Familiarity with multi-voltage and multi-clocking domain implementation is a plus.
• Exposure to advanced approaches including hierarchical DFT and streaming fabric.
• Strong post-silicon experience as it relates to debugging silicon behavior and test-escape issues. Is able to solve difficult problems with creative solutions or analysis.
• Crisp written and oral communication skills including working with global stakeholders
• Thrives in fast-paced environment: i.e. yearly project tapeouts

U.S. Export Control

This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.

Role and Responsibilities

As a highly experienced DTCO engineer, you will help propel Samsung SARC/ACL’s innovation forward by building highly efficient design and analysis flows and methodologies for DTCO. With strong expertise in digital design flows spanning synthesis, PnR, EM/IR, STA, PV and large-design space exploration, you will drive collaboration with the IP development teams to ensure process technology, design rule, standard cell design and design methodology changes are consumable throughout the product development cycle to meet or exceed product key performance indicators.

• You are an innovator. You are skilled at developing CAD flows for custom design with a mindset to continuously push the PPA(power/performance/area)envelope on aggressive designs with a high level of automation for DTCO needs.

• You have a curious mindset and thrive on navigating the unknown through innovation and continuous learning. You will explore a methodology to achieve low-power and high-performance goals for Samsung-specific SOC design styles.

• You have expertise in one or many technical areas, including concepts of logic/physical synthesis, automated place and route, power estimation, and standard cell design.

• You are a problem solver. You enjoy solving CAD and design methodology-related challenges and creating analysis methodologies and metrics most relevant to removing bottlenecks for improvement.

• You thrive in a production and result-oriented environment, working on high-impact, large-scale projects that have a global impact.

• You are skilled at working effectively with various stakeholders by using clear and precise communication skills for technical requirements and specifications, while proactively driving collaboration with cross-functional teams.

• You are detail oriented. You can provide and maintain thorough documentation, publish results, and fulfill other project management-related needs.

• You are a self-starter and driver. You enjoy seeking new problems and owning solutions to drive toward production.

Skills and Qualifications

• 15+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 13+ years of experience with a Master’s Degree, or 11+ years of experience with a Ph.D.

• 10+ years of custom design tools and methodology development experience.

• 10+ years of experience with industry standard automated design tools for synthesis, place and route, EM/IR analysis, static timing analysis and/or physical verification.

• 10+ years of experience working with Cadence Innovus and/or Synopsys Fusion Compiler and reference flows.

• Experience with PPA analysis across standard cell library, memory compiler, interconnect stack options and block-level PPA evaluation.

• Strong knowledge of CMOS fundamentals, device physics, device-technology interactions, scaling trends, and design and implementation challenges at advanced technology nodes.

• Experience working with batch run oriented environments for design space exploration and high throughput.

• Experience working with foundries is a plus.

• Experience in improving productivity, efficiency and/or quality of results through machine-learning (ML) practices is preferred.

• Strong skills withscripting/programminglanguages like Tcl, Perl, Python.

• Strong data analysis skills to analyze and deduce information from large data sets and apply the learnings to other scenarios.

U.S. Export Control

This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.

Role and Responsibilities

• Manage projects related to incoming technology transfer, new product introductions, yield improvement, stop loss reduction, cycle time reductions and other KPI improvements.

• Design, execute, and analyze experiments.

• Uses software to analyze data including statistical analysis; Consults with leadership team on experimental results in order to make decisions about large-scale changes.

• Responsible for critical or complex steps or layers in the wafer fabrication process.

• Trouble shooting issues affecting Yield, defect, electrical performance of products

• Develops Change Point Management Plans.

• Communicates technical information with presentation.

Education, Training, Certification(s) and Minimum # Years Required:

• Bachelor’s degree in Physics, Chemistry, Electrical Engineering, Chemical Engineering, Materials Science or related field is required.

• Master's or Ph.D. is preferred.

• Basic understanding of some unit processes including thin films deposition, lithography, etch, diffusion, wet process, Cu plating, and CMP.

• Basic understanding of the interactions between process and yield.

• Electrical Engineering, Materials Sciences, and Physics expertise within semiconductor field is required.

• Must have basic understanding of Semiconductor process flow in assigned areas.

• Experience in Yield or Process Integration in semiconductor manufacturing is strongly preferred.

• Experience with Foundry Customer communication is strongly preferred.

• Experience with development is strongly preferred.

• Experience with DDI Process Integration is preferred.

Note: This position is Full-Time onsite.

We offer a comprehensive benefits package, including:

• Medical, dental, and vision insurance
• Life insurance and 401(k) matching with immediate vesting
• Onsite café(s) and workout facilities
• Paid maternity and paternity leave
• Paid time off (PTO) + 2 personal holidays and 10 regular holidays
• Wellness incentives and MORE
  

All positions at SAS are full-time on-site.

This role requires access to information subject to U.S. export control laws. Applicants must be authorized to access such information or eligible for government authorization.

Role and Responsibilities

Bachelor’s degree in Computer Networks, Electronics and Communications Engineering, Electrical Engineering, Computer Science, Telecommunications Engineering, a related field, or foreign equivalent and 5 years of progressively responsible post-baccalaureate experience in job offered or any related engineering roles.

Applicants must have 5 years of experience in the following: (1) telecommunications engineering; (2) 4G/5G Call Processing including RRC, S1-MME, S1-U, X2, RLC, MAC, PHY protocols; (3) wireless technology & procedures including LTE/Volte and 5G; (4) 3GPP RAN product architecture, design, implementation and performance improvements (KPIs); (5) RF antenna technologies & network optimizations; (6) Massive MIMO, New Waveforms, LTE-NR interworking & co-existence, and 5G Numerologies; and (7) system engineering activities including feature requirements identification, feature description documentation, parameter optimization, performance analysis, test strategy creation, and problem troubleshooting.

Role and Responsibilities

Audit, execute, or approve Engineering requests to manage content in Samsung systems
• eSPEC: Process specs (STEPSEQ, PPID, queue times, rework, etc.)
• eSPEC: Target specs (Target, USL, LSL, grade, etc.)
• wGPM
Troubleshoot open-ended issues with the systems above in conjunction with interdepartmental teams
Develop SOPs, workflows, and training materials to improve both team and site practices

Skills and Qualifications

• Successful candidates have transferred from UP Process Tech positions or support groups (QR/HRD).
• 2-year Technical Degree preferred, but not required.
• Prefer 2+ years’ experience with database entry, basic database administration and / or auditing (strong knowledge of Microsoft Excel).
• 1+ years’ experience with wGPM, eSPEC, metrology (CD, OCD, TOX), and / or MGuides is a plus.
• Background in coding is a plus (no specific coding is required for this position).

We offer a comprehensive benefits package, including:

• Medical, dental, and vision insurance
• Life insurance and 401(k) matching with immediate vesting
• Onsite café(s) and workout facilities
• Paid maternity and paternity leave
• Paid time off (PTO) + 2 personal holidays and 10 regular holidays
• Wellness incentives and MORE
  

All positions at SAS are full-time on-site.

This role requires access to information subject to U.S. export control laws. Applicants must be authorized to access such information or eligible for government authorization.

Role and Responsibilities

Bachelor’s degree in Computer Networks, Electronics and Communications Engineering, Electrical Engineering, Computer Science, Telecommunications Engineering, a related field, or foreign equivalent and 5 years of progressively responsible post-baccalaureate experience in job offered or any related engineering roles.

Applicants must have 5 years of experience in the following: (1) telecommunications engineering; (2) 4G/5G Call Processing including RRC, S1-MME, S1-U, X2, RLC, MAC, PHY protocols; (3) wireless technology & procedures including LTE/Volte and 5G; (4) 3GPP RAN product architecture, design, implementation and performance improvements (KPIs); (5) RF antenna technologies & network optimizations; (6) Massive MIMO, New Waveforms, LTE-NR interworking & co-existence, and 5G Numerologies; and (7) system engineering activities including feature requirements identification, feature description documentation, parameter optimization, performance analysis, test strategy creation, and problem troubleshooting.