דרושים Windows Driver Development Engineer ב-Samsung ב-India, Bengaluru

Role and Responsibilities

component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, StorageSolutions, AI/ML,5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.

Roles and Responsibilities

5+ years of experience in full chip DFT architecture, implementation, timing closure and post silicon validation. Expertise required in the following areas:

• Scan architecture planning, pin mixing and scan compression planning, optimization for pattern volume for SA and TD pattern sets, scan synthesis, power optimization techniques in test modes
• MBIST architecture planning, repair architectures, insertion, verification
• Analog and mixed signal IP testing architecture and verification including IPs such as PLLs, PHYs
• Timing closure of scan, MBIST and other test modes, writing SDCs, understanding of timing exceptions wherever required, debugging timing issues with PD team
• Timing GLS, debug of fails in simulations
• Post silicon validation, interpretation of tester results, debugging IR drop issues, diagnostics of silicon failures
• Understanding of JTAG operation and debug required. Understanding of iJTAG protocol desirable
• Understanding of functional test cases, IO testing, testing of ARM processor cores

Qualifications

Role and Responsibilities

• Design highly competetive circuits to meet peroformance/power specificiations requested by customers
• Guide and lead a group of engineers to deliver the SRAM IP in the given timelines
• Analyse circuits and indentify potential robustness gaps and find solutions to improve robustness of the design.

• Own the responsibility from SPEC to GDS and DK delivery.
• Review circuits, robustness reports and identify potential robustness issues.
• Review Layouts and suggest improvement areas to achieve competitive PPA
• Understanding of SRAM PPA trade-offs and identify right techniques to meet SPEC
• Must be able to communicate effectively across different teams.

Skills and Qualifications

• Master/Bachelor in electronics
• Working experience (10+years) in preferably Memory design
• Understanding of RC network and finfet fundamentals are necessary.
• Custom or Compiler SRAM/ROM development experience
• Fundamentals of process variability and its effect on memory design
• Thorough understanding of SRAM bit cell and its characteristics (Read current, Standby current, data retention, SNM)

• Stong understanding of circuit design fundamentals
• Critical path modeling concept, various type of models ( RC, C, Pai, ladder)
• Good knowledge of semiconductor physics. Like knowledge of finfet function, parasitics etc
• Analysing layout and understanding of LLE effects.

• Bachelor's /Master degree in Computer Science,Electrical/ElectronicsEngineering, Engineering and 10+ years of experience in circuit design.

Role and Responsibilities

component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, StorageSolutions, AI/ML,5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.

Roles and Responsibilities

• To Develop (System-Core/PowerManagement/Connectivity/Storage/Display / Ethernet/ IVI/HUD) Device drivers for ARM based Exynos Chipsets.
• Working knowledge of Linux / QNX device drivers
• Good knowledge of Linux kernel and device driver development
• Good experience with Bootloader, I2C, PMIC, UART, SPI, USB, UFS, MMC Power or similar device drivers.
• System level knowledge and experience in Board bring up and debugging.
• Good Knowledge of Debug tools and power and performance optimization.
• Good Knowledge of LinuxInternals/Frameworks/ARMArchitecture.
• Manage Samsung Exynos BSP / Device Driver Deliverables.
• Experience in Linux/Android BSP development at product level
• Knowledge on Linux/Android Power management framework Suspend/Resume.
• Knowledge on Runtime PM, CPU freq/Idle scaling governors, DVFS.
• Knowledge of ARM/CPU Architecture, cache and Linux scheduler is desirable.
• Ability to resolve system level power/performance issue during product development
• Experience in analyzing system level performance bottlenecks and fixing bench mark scores

Good to Have:

• To do the bring up of the latest Android Platform on these devices and product development with Latest Exynos SoCs.
• To involve in the development of the commercial phones with latest Android Releases and provide upgrades .
• To Provide customer support to different vendors who are making products with Exynos Family chipsets (Mobile/Wearables).
• Android HAL development Infotainment Media, Phone, Camera, BT, radio, Vehicle (anyone is fine)
• Good understanding of Android architecture and internals (AOSP, Binder IPC, HAL & Native services)
• Working on Android HAL layer and realizing various customer requirements on Android.

6 to 10 Years

Qualifications

Role and Responsibilities

component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, StorageSolutions, AI/ML,5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.

Roles and Responsibilities

Complex SOC Top Physical Implementation for next generation SOCs in area of mobile application processors, modem sub-systems and connectivity chips by means of Synthesis , Place and Route, STA , timing and physical signoffs

• Hands on experience doing physical design and timing closure of complex blocks and full-chip designs.
• Experience in top level floor planning including partition shaping and sizing, pin placement, channel planning, high speed signal and clock planning and feed-through planning is a plus.
• Should have strong understanding of timing, power and area trade-offs and optimization of PPA.
• Power user of industry standard tools(ICC/DC/PT/VSLP/Redhawk/Calibre/Formality)and able to understand their capabilities.
• Should have solid understanding of scripting languages such as Perl/Tcl and implementation flows.
• Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ .
• Expertise in block level and full-chip SDC clean up, Synthesis optimization , Low Power checking and logic equivalence checking.
• Familiar with deep sub-micron designs (8nm/5nm) and associated issues (manufacturability, power, signal integrity, scaling).
• Familiar with typical SOC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions.
• Familiar in hierarchical design, top-down design, budgeting, timing and physical convergence.
• Good understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level.
• Should have gone through recent successful SOC tape-outs.

Qualifications

Role and Responsibilities

component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, StorageSolutions, AI/ML,5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.

Roles and Responsibilities

Independent Verification Ownership of IP DV.

Expected to work hands on to close all aspects of verification activities including Testplan creation, building testbenches based on standard DV methodology , developing DVInfrastructure(Coverage/Regression/SimulationScripts)

Must have experience in developing test benches for IP/Subsystems/SoC.

In depth knowledge and hands on experience in the execution of verification of SoC/SS/IP DV

Previous experience of independently driving IP DV projects from Ability to lead a team by providing technical guidance as well as by part of execution by debugging and SoC architecture understanding capabilities

Strong hands on experience with common verification tools and methodology including UVM/System Verilog/CDV/MDV, DV signoffs.

Must have a strong domain expertise in one or more following areas -
CPU/Cache Coherency/CPUPipeline/Cache/BranchPrediction/MMU

Experience in Hybrid testbenches(SV, C/C++, Python) and C/C++ based CPU vectors/stimulus based verification is desirable.

Experience/Exposure to RISC-V Core DV or any other Core DV s highly preferred

Qualifications

Role and Responsibilities

5 to 14 years of work experience in VLSI RTL IP or Subsystem design

JobDescription/background:

· Designing and developing CXL and DRAM controller (DDR4/5) based intellectual property.

-Design and Engage with other architects within the IP level to drive the Micro-Architectural definition.

· Deliverquality micro-architectural level documentation.

· Producequality RTL on schedule by meeting PPA goals.

· Beresponsible for the logic design/ RTL coding [in Verilog and/or System Verilog], RTL integration, and timing closure of blocks.

· Collaboratewith the verification team to ensure implementation meets architectural intent.

· Hands-onin running quality checks such as Lint, CDC and Constraint development.

· Substantialbackground in debugging designs in the simulation environments.

· Deepunderstanding of fundamental concepts of digital design

Preferred Skill:

· StrongVerilog/System Verilog RTL coding skills.

· Experience with DRAM Memory Conytroller design.

· Knowledge of DRAM standard (DDR4/5) memory.

· Interface/Protocolexperience required - AHB/AXI, Processor local bus, Flash, SPI, UART,etc.·

· Experiencewith Xilinx/Intel FPGA Tool flow

· Knowledgeof PCIe/PIPE

· Knowledgeof projects with (Microblaze, ARM cores, etc.)

· Knowledgeof CXL Protocol is appreciated.

Skills and Qualifications

Master’sdegree or Bachelor’s degree in Electronics or Electrical Engineering.

· 5to 14 years of relevant work experience in RTL design & Integration, Synthesis, and timing closure.

Role and Responsibilities

component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, StorageSolutions, AI/ML,5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.

Roles and Responsibilities

Experience using parallel programming APIs and languages such as OpenCL or CUDA

• Knowledgeable in GPU or other parallel processing architectures , Strong knowledge of GPU architecture.
• Knowledge of APIs such as Vulkan, Open GS ES 3.x, DX 11/12, OpenCL and other compute APIs ,UMD/ KMD.
• Knowledge of key mobile GPU graphics workloads and compute application workloads such as computer vision, image processing, AI and Image compression.
• Knowledge of game applications, game rendering engines, academic papers on advanced rendering techniques desirable.
• Expertise in implementing advanced graphics rendering techniques, machine-learning (AI) approaches.
• Proven ability to debug complex issues in multi-threaded environments.
• Understanding of Operating System fundamentals and concepts.
• Familiarity with offline and JIT compiler designs.
• Background in Linux and Android development.
• Strong C, C++ and Python programming experience of industrial experience in systems programming (driver development a strong plus).
• Strong algorithmic background.

Qualifications