Samsung DFT Design Engineer - Foundry Team 

India, Karnataka, Bengaluru 

499553848

Role and Responsibilities

component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, StorageSolutions, AI/ML,5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.

Roles and Responsibilities

5+ years of experience in full chip DFT architecture, implementation, timing closure and post silicon validation. Expertise required in the following areas:

• Scan architecture planning, pin mixing and scan compression planning, optimization for pattern volume for SA and TD pattern sets, scan synthesis, power optimization techniques in test modes
• MBIST architecture planning, repair architectures, insertion, verification
• Analog and mixed signal IP testing architecture and verification including IPs such as PLLs, PHYs
• Timing closure of scan, MBIST and other test modes, writing SDCs, understanding of timing exceptions wherever required, debugging timing issues with PD team
• Timing GLS, debug of fails in simulations
• Post silicon validation, interpretation of tester results, debugging IR drop issues, diagnostics of silicon failures
• Understanding of JTAG operation and debug required. Understanding of iJTAG protocol desirable
• Understanding of functional test cases, IO testing, testing of ARM processor cores

Qualifications