Samsung RTL Micro-Architecture Design Engineer DRAM Controller_TB5-TB7_DRAM_Memory 

India, Karnataka, Bengaluru 

943639758

Role and Responsibilities

5 to 14 years of work experience in VLSI RTL IP or Subsystem design

JobDescription/background:

· Designing and developing CXL and DRAM controller (DDR4/5) based intellectual property.

-Design and Engage with other architects within the IP level to drive the Micro-Architectural definition.

· Deliverquality micro-architectural level documentation.

· Producequality RTL on schedule by meeting PPA goals.

· Beresponsible for the logic design/ RTL coding [in Verilog and/or System Verilog], RTL integration, and timing closure of blocks.

· Collaboratewith the verification team to ensure implementation meets architectural intent.

· Hands-onin running quality checks such as Lint, CDC and Constraint development.

· Substantialbackground in debugging designs in the simulation environments.

· Deepunderstanding of fundamental concepts of digital design

Preferred Skill:

· StrongVerilog/System Verilog RTL coding skills.

· Experience with DRAM Memory Conytroller design.

· Knowledge of DRAM standard (DDR4/5) memory.

· Interface/Protocolexperience required - AHB/AXI, Processor local bus, Flash, SPI, UART,etc.·

· Experiencewith Xilinx/Intel FPGA Tool flow

· Knowledgeof PCIe/PIPE

· Knowledgeof projects with (Microblaze, ARM cores, etc.)

· Knowledgeof CXL Protocol is appreciated.

Skills and Qualifications

Master’sdegree or Bachelor’s degree in Electronics or Electrical Engineering.

· 5to 14 years of relevant work experience in RTL design & Integration, Synthesis, and timing closure.