דרושים Nvidia Internships Hardware Verification ב-אנבידיה ב-ארהב

What you’ll be doing:

• Technical leadership role todefine/plan/implement/executeperformance verification strategy of sophisticated CPU designs

• Ability to delve into lowest level details of CPU unit design specification, implementation and it's performance impact

• Interactions with architect and design engineers to define detailed scope of micro architectural features

• Draft detailed performance testplans and define/Create scalable micros to validate features

• Analysis and correlation of CPU benchmarks/workloads

• Build infra/tooling needed for efficient performance correlation debug

• Ability to lead and provide detailed technical guidance to junior engineers

• Agility to work on multiple tasks/projects

What we need to see:

• BS or MS in EE/ECE or equivalent experience. PhD is a plus

• 3+ years of experience in CPU performance modeling, performance correlation, performance analysis, or relevant experiences

• Strong understanding in CPU micro architecture and designs

• Experience with workload analysis and characterization

• Strong coding skills in scripting languages like Perl, Python, or C++

• Good communication skills and ability & desire to work as a team player are a must

Ways to stand out from the crowd:

• Experience leading performance validation of major blocks of CPU pipeline

• Background with ARM A64, X86 Architectures

• Be an integral part of the team defining, developing, and delivering system-level methodologies and RTL to measure performance on the industry's leading GPUs and SOCs

• Define, develop, and automate flows and methodologies to efficiently build, deliver, and support a system-level IP

• Deliver IP and support projects by applying the performance monitoring system

• Run and debug RTL checks to ensure design quality (e.g., cross clock domains (CDC), clocks, reset, latency, and more)

• Design and implement RTL features (microarchitecture and RTL)

• Work with architects, designers, and software engineers to accomplish your tasks

• BS or equivalent experience in Electrical Engineering, Computer Engineer, or related degree required, advanced degrees (MS, PhD) a plus

• 3+ years of relevant industry experience and strong coding skills in Perl/Python or other industry-standard scripting languages

• Experience in RTL design (Verilog), verification (SystemVerilog), System-On-Chipdesign/implementationflow, and design automation

• Good understanding of SOC architecture, including CDC, multiple-power domains, performance analysis, latency, and data flow

• Excellent debugging and analytical skills

• Exposure to design and verification tools (dc_shell or equivalent synthesis tools, VCS or equivalent simulation tools, debug tools like Debussy, GDB)

• Great communication and collaboration skills to interact within the team and with cross-functional teams

• Hands on experience in object-oriented programming

• Prior design on system level IP (Clocks/DFT/Resets)

• Experience developing methodologies used by others

• Hands- on silicon debug is a plus.

• Exposure to physical design

What you'll be doing:

• Develop and deploy in-house tools and workflows to support engineering business units across NVIDIA.

• Take ownership of tools that verify common design blocks used in all products at NVIDIA.

• Act as a "DevOps" engineer for automated RTL generation by developing new features and maintaining efficient operations for existing users.

• Build new workflows and methodologies to ensure smooth integration into various IP development environments.
  

What we need to see:

• Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering (or equivalent experience).

• 3+years of proven experience preferred.

• Solid understanding of fundamental digital design concepts with hands-on experience in Verilog.

• Proficiency in scripting using modern Python and/or Perl.

• Experience with Unix/Linux shell scripting and Makefiles.

• Strong ability to collaborate with multi-functional teams and effectively communicate technical details.

Ways to stand out from the crowd:

• Prior experience in ASIC verification.

• Knowledge of Clocks/Resets design and verification.

• Exposure to CDC related design/verification flows.

• Exposure to backend flows (Synthesis, Timing, etc).

What you will be doing:

• Work in a combined design and verification team which develops core units within the Networking silicon.

• Build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.

• Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, FW and Post-Silicon validation.

• Lead the verification effort for core switching fabrics, packet buffering architectures, and traffic management subsystems, ensuring functional correctness and performance at scale.

What we need to see:

• B.SC./ M.SC. in Computer Engineering /ElectricalEngineering/CommunicationEngineering or equivalent experience

• 8+ years of proven experience in Design Verification.

• Proven, hands-on experience verifying sophisticated network switching ASICs, with deep knowledge of core switching logic and advanced buffering architectures

• Demonstrated ability to own verification strategy and execution from the block-level through full-chip (SoC) integration.

• Sharp analytical and debugging skills with a track record of root-causing complex hardware, testbench, or software-driven issues.

• Excellent organizational and communication skills, with the ability to manage priorities and negotiate solutions across design, verification, and architecture teams.

Ways to stand out from the crowd:

• Deep experience verifying advanced traffic management (TM) and Quality of Service (QoS) features, such as complex schedulers, shapers, and congestion control mechanisms

• Proven experience building performance-focused verification environments to measure and stress test latency, throughput, and fairness

• Knowledge in SimVision and Xcelium

ATE/SLT hardware team provides the interface hardware of IC package testing at final test and system level test. Hardware includes highly custom high-speed sockets, active thermal plungers, and load boards. Take an active role in hardware design for both product bring-up and HVM, design and manufacture improvement, and verification/debug, to production support.

What you’ll be doing:

• Review and approve the design of test socket, thermal plunger, and other accessories related to ATE/SLT IC testing for product bring-up and production.

• Provide ATE and SLT test fixture/HW solutions from design, manufacturing order, schedule monitoring, verification, and improvement.

• Drive ATE and SLT socket/thermal technology, solutions, and qualifications.

• Drive DOE with a sense of responsibility from collecting and analyzing engineering data and making decisions and recommendations for improvement.

• Provide cross-functional support.

• Drive a project and host a meeting internal and external stakeholders.

• Apply strong hardware troubleshooting and root-cause analysis. Possess the ability to provide preventive actions.

• Able to debug ATE/SLT hardware setup such as socket, thermal plunger, PCB, chiller, and handler.

• Require on-duty lab support. Weekend support may be necessary.

What we need to see:

• Bachelor’s degree or equivalent experience is required. EE and ME related degrees are preferred.

• 5 plus years of IC testing engineering and ATE/SLT hardware engineering experience.

• Having test socket knowledge is a strong plus. Familiar with test socket mechanics, footprints, and contact pins.

• Fully capable of understanding mechanical drawings and knowing mechanical and electrical circuit knowledge.

• Have IC testing knowledge of ATE/SLT interface hardware, maintenance, troubleshooting, and repairs. (Socket, load board, thermal plungers)

• Having ATE tester knowledge is a plus.

• Proven troubleshooting skills and ability to provide solutions and prevent reoccurrence.

• Willing to conduct hands-on-work such as socket pin repair, electric wire, and tiny capacitor/resistor.

• Able to lift 30 pounds load board during unboxing, boxing, and a short transportation.

• Have the knowledge of prevention and control of electrostatic discharge (ESD)

What you'll be doing:

• Performing physical layout for mixed-signal functions like PLL's, high speed SerDes, Analog to Digital converters, ESD structures designs in groundbreaking sub-micron CMOS technologies using Cadence tools.

• You'll work cross functionally with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.

• Take part in floor planning, custom layout and verifying against design rules and schematics.

What we need to see:

• Have a BSEE or equivalent experience.

• Minimum of 7+ years proven experience in Mask and Layout Design.

• Deep understanding of analog circuit layout concepts in submicron CMOS technologies.

• You are an authority with Cadence custom circuit design tools - particularly virtuoso.

• Experience running and debugging with verification tools such as Dracula, Hercules, Calibre, and Primeyield.

• You are able to work optimally in a team, good interpersonal skills, passion and positive energy.

• Proficient in scripting languages like perl, python, skill etc.

• Should have knowledge of DRC and LVS checking flows, ability to customize decks.

What you'll be doing:

• Leading the end-to-end product lifecycle, from new features to supporting new AI platforms, delivering multiple releases per year.

• Collaborating with cross-functional teams, including engineering, marketing, and sales, to successfully implement product strategies and roadmaps.

• Writing clear requirements, user stories, and compelling user experiences to ensure a quality product.

• Managing release schedules and coordinating with development teams to ensure timely delivery of enterprise software products.

• Applying sophisticated product management software to monitor progress, track metrics, and report on the success of product initiatives.

What we need to see:

• Bachelor's degree in Computer Science, Engineering, or equivalent experience.

• Minimum of 8 years of experience in software product management.

• Extensive hands-on experience with compute, network, and storage technologies.

• Proven proficiency in release management strategies and adept utilization of product management software tools.

• Proven written and verbal communication skills. Ability to effectively connect with technical and non-technical stakeholders.

• Leadership skills! Remove obstacles. Resolve ambiguity. Comfortable presenting and defending your fact-based opinion or recommendation.

Ways to stand out from the crowd:

• Hands-on experience with NVIDIA Base Command Manager or Bright Cluster Manager

• Experience as an SRE, datacenter operator, infrastructure manager

• Experience with high-performance computing

• Background with Software Development Life Cycle