דרושים Senior Staff Engineer Physical Design ב-Marvell ב-Vietnam, Ho Chi Minh City

What You Can Expect

What We're Looking For

What You Can Expect

Marvell is seeking an Analog Design Engineer to contribute to the development of multi-tens of GHz Serdes related circuit. These leading edge Serdes IPs are used in multiple products and systems.
• Candidate will be responsible for active circuit design.
• Design leading edge Serdes related circuits, which circuit performance will need to transcend beyond industry leading products.
• Develop transmission line structures to enable higher performance than would normally be achievable.
• Design of various other analog circuits including linear regulators, AGC loop, current/voltage sensors, bandgaps etc.

What We're Looking For

• MSc/PhD EE in the areas of design of high-performance analog/mixed-signal ICs with >5 years of experience.
• Proven experience in IC design including chip tape-out AND lab evaluation of design
• Performing Analog Custom Layout
• Experience in measuring IC performance and debug of design to correlate simulations to measurements
• Deep understanding of fundamental, including:
- Detailed transistor level design
- Device physics
- Control/Feedback loop stability analysis

- FinFet design and layout experience
• Direct project experience in at least one of the following areas a plus:
- AGC loop design
- High precision analog circuits (Including linear regulators, current sensors, bandgaps and DAC/ADC)
- Serdes related design
• Experience in Package-System integration issues desired
• A team-player
• Strong communication, presentation and documentation skills.

What You Can Expect

- Develop UVM testbench at block level and SOC level for complex ASIC System-On-Chips

- Run RTL and gate-level functional verification, debug failures, analyze and improve functional and code coverage

- Develop and improve the verification flow and methodology

What We're Looking For

- BS/MS in Electrical, Computer, or Computer Science with high GPA score.

- 8+ years of experience in ASIC verification.

- Knowledge of ASIC design and verification flow including RTL design, simulation, synthesis, test bench development, regression.

- Knowledge of System Verilog - Knowledge of UNIX environment, Perl, Shell scripting.

- Knowledge of verification methodology such as UVM/OVM/VMM, define verification approach, and verification plans.

- Knowledge of SSD/NAND/NVMe background knowledge.

- Knowledge of CPU subsystem.

- Knowledge of DDR/PCIE/SATA/SAS standard is a plus - Good written and oral communication skills in English.

What You Can Expect

• Work on all aspects of DFT (Design for Testability) for networking domain products, including architecture, testability strategy, flow, implementation, verification, and post-silicon bring-up.
• Collaborate with DFT team members for feature implementation, integration, and verification in SoCs.
• Work closely with Logic Design, Physical Design, STA, and ATE teams to ensure seamless DFT execution.

What We're Looking For

• Bachelor's/Master's degree in Electronics, Electrical Engineering or related fields and a 5 to 10 years of related professional experience in DFT.
• Strong expertise in Memory BIST with knowledge of memory testing, fault models, and BIST techniques.
• Experience in Tessent MBIST block and SoC implementation.
• Hands-on experience in MBIST simulations, production pattern generation, and mode constraints.
• Cross-functional collaboration with DFT, design, synthesis, physical design, and STA teams.
• Knowledge of JTAG (IEEE 1149.1/6 standards) and post-silicon ramp-up/debug on ATE.
• Experience with gate-level simulations (no timing & SDF-based simulations).
• Proficiency in MBIST insertion tools (Mentor Tessent preferred).
• Additional experience in SCAN, ATPG, and JTAG is a plus.
• Strong Perl/Tcl scripting skills.
• Excellent teamwork, communication, ownership, and responsibility for successful tape-out and post-silicon ramp-up.​

What You Can Expect

• Collaborate with the Architecture team to define the micro-architecture of the chip.
• Develop specifications and micro-architecture for one or more blocks.
• Implement RTL coding using best practices.
• Work with physical design teams for synthesis and timing signoff.
• Partner with verification teams on test plans, coverage analysis, and debugging.
• Support post-silicon validation for production qualification.
• Coordinate with project managers on task allocation and mentorship.
• Engage with multiple design centers to enhance methodologies.
• Collaborate with software teams to ensure compatibility with software use cases.
• Mentor and provide technical guidance to junior engineers.

What We're Looking For

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 12-15 years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 10-12 years of experience.
• Micro-architecture experience for complex Custom/ASIC products.
• Strong logic design and debugging skills; expertise in AHB, AXI, I2C, UART.
• Hands-on RTL design, synthesis, timing closure, formal verification, and gate-level simulations.
• Knowledge of PCIe, SPI, USB, DDR2/DDR3 is a plus.
• Proficiency in front-end design tools and methodologies.
• Scripting skills in Perl, Tcl, UNIX shell are a plus.
• Strong leadership, communication, and problem-solving skills.
• Ability to thrive in a fast-paced environment and drive team success