Marvell Senior Engineer Analog IC Design 

Vietnam, Ho Chi Minh City 

310247535

What You Can Expect

- Develop UVM testbench at block level and SOC level for complex ASIC System-On-Chips

- Run RTL and gate-level functional verification, debug failures, analyze and improve functional and code coverage

- Develop and improve the verification flow and methodology

What We're Looking For

- BS/MS in Electrical, Computer, or Computer Science with high GPA score.

- 8+ years of experience in ASIC verification.

- Knowledge of ASIC design and verification flow including RTL design, simulation, synthesis, test bench development, regression.

- Knowledge of System Verilog - Knowledge of UNIX environment, Perl, Shell scripting.

- Knowledge of verification methodology such as UVM/OVM/VMM, define verification approach, and verification plans.

- Knowledge of SSD/NAND/NVMe background knowledge.

- Knowledge of CPU subsystem.

- Knowledge of DDR/PCIE/SATA/SAS standard is a plus - Good written and oral communication skills in English.