דרושים Engineering Project Management Principal Engineer ב-Marvell ב-India, Bengaluru
Marvell Senior Staff Engineer Verification India, Karnataka, Bengaluru
What You Can Expect
- Provide co-design support with both ESD simulations of circuits to maximize both performance and ESD protection robustness.
- Perform ESD design reviews and provide the required technical guidance for analog, foundational IP, SOCs, and qualification test chips for multiple technology nodes ranging from 45nm to 2nm across major foundry platforms.
- Validate and characterize ESD circuits using ICV PERC, Calibre PERC, TLP-based SPICE simulation, and any other industry methods and tools.
- Design enablement of ESD protection schemes for analog design like SerDes. This will include understanding ESD protection design, latch-up, transient latch-up as well as ESD design verification and EDA tools.
- Continue the development of “best practices” for ESD in the technologies being supported.
- Development and support of EDA tools for ESD design checking.
- Development of circuits like Driver, Receiver, Overvoltage protection circuits, Fail safe I/O, Bandgap and Voltage Regulators.
What We're Looking For
- Bachelor’s or Master’s degree and/or PhD inElectrical/ElectronicEngineering, Microelectronics or related fields and 8-15 years of related professional experience.
- Expertise in custom circuit design, handling layout effect in advanced FinFET process design rules, process variability and circuit reliability issues that affect power, speed, area, and yield.
- Advanced knowledge of on-chip ESD protection circuit design
- Advanced knowledge of CAD design tools such as Cadence and SPICE
- Applicant should have sufficient design experience to be able to effectively review designs and communicate ESD design deficiencies to product design engineering.
- Advanced knowledge of ESD relevant device physics such as snapback and other high-level injection phenomenon/device operations
- Fully familiar with industry ESD test standards and latest developments.
- Experience with verifying ESD analysis for IP and SoC level using industry standard tools and methodologies.
- Exposure and experience with the Custom ESD PERC code development will have added advantage to this role.
- Experience with simulation skills using cadence including PEX, Monte Carlo, and Corner analysis.
- Derive design specifications from customer requirement.
- Requires effective communication between multiple sites and ability to work with multiple groups.
משרות נוספות שיכולות לעניין אותך
Marvell Principal Engineer RTL ASIC Design India, Karnataka, Bengaluru
What You Can Expect
• Lead DV, emulation and post silicon validation execution with zero defect mindset.
• Define DV, emulation and post silicon validation scope.
• Define execution timelines working closely with stakeholders.
• Set goals, monitor, and take steps to keep the execution on track.
• Define DV methodology and verification strategies.
• Drive definition and implementation of DV TB architectures.
• Collaborate with Architecture, Design, DFT, PD, FW and system teams for successful product execution.
• Lead tool evaluation and selection.
• Drive continuous productivity improvements through incremental and forklift changes.
• Monitoring industry DV trends and adapting to key trends.
• Hire, build and retain high performance engineering team.
• Address continuous training and development needs of the team.
What We're Looking For
• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 10+ years of experience.
• Strong understanding of ASIC development process.
• Proven ability to lead ASIC development teams.
• Demonstrated track record of delivering high quality ASICs.
• Good understanding of SoC architecture, processor cores, memory, and peripheral interfaces.
• Excellent communication, interpersonal and presentation skills.
• Strong cross-functional leadership skills.
• Highly motivated, self-driven and curiosity to learn new technologies.
Expected Base Pay Range (USD)
203,000 - 300,480, $ per annumThe successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at
משרות נוספות שיכולות לעניין אותך
Marvell Principal Staff Software Validation Engineer L1 Embedded sys... India, Karnataka, Bengaluru
What You Can Expect
- Develop and implement compensation strategies for the Americas region that align with the company's goals and market trends.
- Provide expert guidance and support to HR partners and business leaders on compensation-related matters.
- Monitor and analyze compensation data to identify trends, issues, and opportunities for to ensure competitive and equitable compensation and drive improvement within the Americas region.
- Ensure compliance with local labor laws and regulations related to compensation across the Americas.
- Collaborate with People Analytics and HRIS teams to enhance compensation data analytics and reporting capabilities.
- Manage key compensation projects and initiatives from inception to completion, including developing project plans, setting timelines, and allocating resources effectively.
- Develop and deliver training on compensation practices and policies to HR partners and business leaders within the region.
- Stay updated on industry trends and best practices in compensation.
What We're Looking For
- 5 – 10 years of experience working in large corporate compensation role.
- Bachelor’s degree in business, arts, science or related field
- Strong analytical and data interpretation skills
- Strong collaboration and communication skills.
- Strong English language skills
- Proficiency in HRIS, particularly Workday.
משרות נוספות שיכולות לעניין אותך
Marvell Senior Staff Serdes Validation Engineer India, Karnataka, Bengaluru
What You Can Expect
Experience in the following and not inclusive of:
Day to day management of physical security measures atglobal headquarters andassigned region(reporting, investigations, event coverage assignments, access control measures, emergency response,ensuringaccess control andcamera systems are functioning andsupportingremediation)
Fostering relationships with site assigned POCsfor collaboration and provide remoteassistanceas warranted
Implementation of strategies by senior management (emphasis on execution of andmaintainsecurity measures such as access controls, surveillance systems, and emergency response.)
Manages on-sitecontractsecurity teams that fall under j. (i.e., work with vendors in their sphere of influence to ensure no violation of co-employment legalities and report accordingly of shortcomings to next level to ensure service standards)
Analysis of costs for each location for roll-up into larger organizational requirements
Handles the on-location security opportunities, such as dealing with immediate risks at assigned locations
Site level problem solving that does not affect larger organization
Incident Response
Team oversight
Policy and Protocols
partments
Training staff and employees
Technical knowledge (access and monitoring systems)
Reporting and investigations
Familiarity with local security regulations
At Marvell Technology, our Global Physical Security team is dedicated to safeguarding our employees, assets, and operations worldwide. As the Physical Security Manager for the Americas region, you will play a crucial role in overseeing and managing security operations across multiple offices. Your leadership will be instrumental in developing and implementing security protocols, conducting risk assessments, managing security personnel, and ensuring compliance with local and international laws. Collaborating with various departments, you will promote a culture of safety and security that enables Marvell to innovate and excel in the semiconductor industry.
Incident Response:Lead and coordinate responses to security incidents, ensuring swift resolution and minimal impact on operations.
Manage and mentor a team of security professionals, fostering a proactive and vigilant security culture.
Policy and Protocols:Develop, implement, and enforce security policies and procedures tomaintaina secure environment.
Work closely with other departments to integrate security considerations into broader organizational initiatives.
Design and deliver training programs to educate employees on security protocols and best practices.
Technical Knowledge:Oversee the operation and maintenance of security systems, including access controls and surveillance systems.
Reporting and Investigations:Conduct thorough investigations into security incidents and provide detailed reports to senior management.
Regulatory Compliance:Stay informed about local security regulations and ensure all security practicescomply withrelevant laws and standards.
What We're Looking For
Proven history in security management and incident oversight within a corporate setting.
Skilled in providing and managing security solutions through innovation and quality.
Interpersonal Skills:Ability tomaintainand develop positive working relationships with stakeholders and end-users.
Operational Expertise:Proficient in operational security management, including leadership, team management, and incident response within a corporate environment.
Sound interpersonal and communication skills, with experience in issue and conflict resolution.
Ability to work under own initiative,demonstratingstrong work ethics and decision-making capability.
Technical Proficiency:Competent in Microsoft Word, Excel, Outlook, and PowerPoint.
System Knowledge:Familiarity with security systems such as access controls, camera surveillance systems, and security software platforms.
Expected Base Pay Range (USD)
110,450 - 165,500, $ per annumThe successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at
משרות נוספות שיכולות לעניין אותך
Marvell Principal Professional Cloud Infrastructure Architect India, Karnataka, Bengaluru
What You Can Expect
Provide the instructions to the layout engineers.
Working with the AE for the IP characterization and validation.
What We're Looking For
Master’s degree or PhD in Electrical Engineering
Strong knowledge on the deep sub-micron CMOS technologies.
Experience in designing mixed signal circuits including ADCs, DACs, RX, TX, PLLs, Filters, Bandgap bias circuits, regulators, and other analog circuits.
Knowledge and Experience on low power and high-speed design techniques.
Excellent problem solving, and analytical skills are essential.
Strong knowledge on IC design CAD tools such as Spectre, Spice, Matlab, Hsim, Verilog, etc.
Lab testing skills to evaluate the prototype unit to the design specification.
Expected Base Pay Range (USD)
128,160 - 192,000, $ per annumThe successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at
משרות נוספות שיכולות לעניין אותך
Marvell Engineering Project Management Principal Engineer India, Karnataka, Bengaluru
The Alaska® portfolio of PHY transceivers, high-speed line cards and DSPs for active electrical cables (AECs) offers optimized form factors, multiple port and cable options, efficient power consumption and simple plug-and-play functionality.
What You Can Expect
As a Hardware and Silicon Validation Staff Engineer at Marvell, you’ll be helping to deliver high bandwidth over long distances.
teams such as digital, analog, firmware, to develop Marvell’s next gen,high-speed networking PHY Serdes IP/ICs.
Work independently and collaboratively in post-silicon validation team, to collect, analyze massive data from bench and drive tuning parameters in silicon to ensure product’s quality.
Characterize electrical parameters and building blocks such as Tx jitters, CDR loops, CTLE, PLL, etc.
Tune internal circuitries such as peaking, bandwidth, FIFO, and adaptation algorithms to optimize product’s operating margin at stressed PVT conditions.
Involve in system level hardware (PCB schematics) and work with SI and layout teams to build engineering boards.
Create, maintain and own bench automation libraries (python) for various of products.
As system engineering team at Marvell, we value your ideas and your work will have a direct impact to the product of company.
What We're Looking For
Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 3-5 years of related professional experience. OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 2-3 years of experience.
Experience in following domains is required – Post-Si Validation, Stress & PVT testing.
Strong analog/mixed-signal knowledge.
Solid understanding of modern high-speed PHY/Serdes.
Solid programming skill in languages such as Python, Matlab, etc.
Strong teamwork and communication skills.
Demonstrates good analysis and problem-solving skills.
Expected Base Pay Range (USD)
102,880 - 154,100, $ per annumThe successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at
משרות נוספות שיכולות לעניין אותך
Marvell Staff Engineer - DFT India, Karnataka, Bengaluru
What You Can Expect
• Lead NoC architecture and configuration work for complex SoCs targeting multi-clock high speed designs.
• Define the micro-architecture of SoCs including its blocks, cores, accelerators, and subsystems.
• Work closely with the architecture, floorplanning, backend, verification, DFT, STA teams and other cross functional teams to produce high quality hardware.
• Develop and write micro-architectural specifications of the design.
• Implement designs using good RTL coding and low power techniques.
• Collaborate with the backend team to close on synthesis, place and route, and timing signoff.
• Collaborate with the verification team on pre-silicon verification tasks such as reviewing test plans, coverage closure, and full-chip simulation debug.
• Plan, scope and time tasks with the project manager.
• Work with post silicon group to resolve any lab issues and successfully bringup silicon.
• Collaborate with the software team to ensure customer use cases requirements are met.
What We're Looking For
• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience.
• Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 10+ years of experience.
• PhD in Computer Science, Electrical Engineering or related fields with 8+ years of experience.
• Must have experience with Network-on-Chip (NoC) architecture and design using Arteris FlexNoC tool.
• Experience with general digital design microarchitecture development is a must.
• Design/RTL experience in Verilog or SV is a must.
• Knowledge of scripting languages, such as PERL, Python
• Experience with high speed, low power, and area optimized designs.
• Experience working with multi-clock designs, DFT, resets, LEC, Lint, etc
• Good learning, problem solving interpersonal and communication skills.
• Must be a team player with a strong can-do attitude.
• Self-motivated team player able to thrive in a fast-paced engineering environment.
Expected Base Pay Range (USD)
168,920 - 253,000, $ per annumThe successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at
משרות נוספות שיכולות לעניין אותך
What You Can Expect
- Provide co-design support with both ESD simulations of circuits to maximize both performance and ESD protection robustness.
- Perform ESD design reviews and provide the required technical guidance for analog, foundational IP, SOCs, and qualification test chips for multiple technology nodes ranging from 45nm to 2nm across major foundry platforms.
- Validate and characterize ESD circuits using ICV PERC, Calibre PERC, TLP-based SPICE simulation, and any other industry methods and tools.
- Design enablement of ESD protection schemes for analog design like SerDes. This will include understanding ESD protection design, latch-up, transient latch-up as well as ESD design verification and EDA tools.
- Continue the development of “best practices” for ESD in the technologies being supported.
- Development and support of EDA tools for ESD design checking.
- Development of circuits like Driver, Receiver, Overvoltage protection circuits, Fail safe I/O, Bandgap and Voltage Regulators.
What We're Looking For
- Bachelor’s or Master’s degree and/or PhD inElectrical/ElectronicEngineering, Microelectronics or related fields and 8-15 years of related professional experience.
- Expertise in custom circuit design, handling layout effect in advanced FinFET process design rules, process variability and circuit reliability issues that affect power, speed, area, and yield.
- Advanced knowledge of on-chip ESD protection circuit design
- Advanced knowledge of CAD design tools such as Cadence and SPICE
- Applicant should have sufficient design experience to be able to effectively review designs and communicate ESD design deficiencies to product design engineering.
- Advanced knowledge of ESD relevant device physics such as snapback and other high-level injection phenomenon/device operations
- Fully familiar with industry ESD test standards and latest developments.
- Experience with verifying ESD analysis for IP and SoC level using industry standard tools and methodologies.
- Exposure and experience with the Custom ESD PERC code development will have added advantage to this role.
- Experience with simulation skills using cadence including PEX, Monte Carlo, and Corner analysis.
- Derive design specifications from customer requirement.
- Requires effective communication between multiple sites and ability to work with multiple groups.
משרות נוספות שיכולות לעניין אותך
