What You Can Expect
• Lead DV, emulation and post silicon validation execution with zero defect mindset.
• Define DV, emulation and post silicon validation scope.
• Define execution timelines working closely with stakeholders.
• Set goals, monitor, and take steps to keep the execution on track.
• Define DV methodology and verification strategies.
• Drive definition and implementation of DV TB architectures.
• Collaborate with Architecture, Design, DFT, PD, FW and system teams for successful product execution.
• Lead tool evaluation and selection.
• Drive continuous productivity improvements through incremental and forklift changes.
• Monitoring industry DV trends and adapting to key trends.
• Hire, build and retain high performance engineering team.
• Address continuous training and development needs of the team.
What We're Looking For
• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 10+ years of experience.
• Strong understanding of ASIC development process.
• Proven ability to lead ASIC development teams.
• Demonstrated track record of delivering high quality ASICs.
• Good understanding of SoC architecture, processor cores, memory, and peripheral interfaces.
• Excellent communication, interpersonal and presentation skills.
• Strong cross-functional leadership skills.
• Highly motivated, self-driven and curiosity to learn new technologies.
Expected Base Pay Range (USD)
203,000 - 300,480, $ per annumThe successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at
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