דרושים Full Chip Layout - Physical Architect ב-אינטל ב-ארהב

Key Responsibilities:

• Lead the co-design of silicon and package, focusing on DDR PHY and mixed signal IP integration for server SOCs.
• Design bump maps, floor plans, and manage area constraints for PHYs, collaborating closely with packaging technical experts.
• Conduct hands-onpackage extractionsand simulations(signal integrity, power integrity)
• Finalize bump-out, floor plan, and area decisions at the end of tech readiness phases.
• Interface with packaging teams on advanced technologies (e.g., C4 bumps, micro bumps, EMIB, hybrid bonding as needed).
• Focus on design, development, and architecture, not process or materials engineering.

Required Experience:

• Experience in both silicon design (preferably mixed signal/analog) and packaging co-design.
• Background in DDR, SOC, or similar high-speed interface development.
• Hands-on expertise with bump mapping, floor planning, and packaging constraints.
• Proven ability to collaborate across silicon and packaging teams, including risk assessment and simulation.
• Familiarity with advanced packaging technologies (hybrid bonding, EMIB, etc.) is a plus but not required.
• Individual contributor or principal engineer level preferred; management experience is not required.
• Experience at leading companies in advanced packaging and PHY design (e.g., Apple, Broadcom, Qualcomm, Micron, AMD, Nvidia).

Qualifications:

• Bachelors in electrical engineering, chemical engineering, mechanical engineering, material science or similar field (Master’s or Ph.D. preferred).
• 10+ years in silicon and packaging co-design

Experienced HireShift 1 (United States of America)US, California, FolsomUS, Arizona, Phoenix, US, California, Santa Clara, US, Oregon, Hillsboro
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

Job Description:

About the Role: We are seeking a highly experienced Senior Software Expert specializing in SoC Power and Performance Architecture to join our innovative team. In this pivotal role, you will leverage your expertise to enhance the power efficiency and performance of our System-on-Chip (SoC) designs. You will collaborate with cross-functional teams to ensure our SoCs achieve optimal performance and power efficiency, while identifying and implementing opportunities for improvement. You will also be setting simulation methodologies and driving those across the teams.

Key Responsibilities:
• Power and Performance Optimization: Lead and drive initiatives to optimize SoC power and performance through advanced software techniques, including firmware tuning, workload analysis, and architectural design modifications.
• Collaboration: Partner with architects, design engineers, validation teams, and marketing to deliver industry-leading SoC solutions, providing software insights and expertise.
• Pre-Silicon Planning: Define and implement detailed power and performance tools and methodologies in the pre-silicon phase, focusing on software architecture and design.
• DevOps Pipeline Establishment: Develop and establish DevOps pipelines for power, performance, and thermal architecture tools and methodologies, ensuring efficient and automated workflows.
• Simulation Technologies: Establish and implement simulation technologies and methodologies to predict and analyze power, performance, and thermal characteristics.
• Simulation Model Development: Develop and refine simulation models for power, performance, and thermal analysis, enabling accurate and predictive assessments of SoC designs.

Qualifications:

Minimum Qualifications:

• Bachelor's degree with 7+ years of experience or
• Master's degree with 5+ years of experience, or
• PhD with 2+ years of experience in Electrical Engineering, Computer Engineering, or a related field.

Preferred Qualifications:

• In-depth knowledge of CPU architecture, benchmarks, power management, and memory sub-system validation.
• Extensive experience in simulation development in the pre-RTL phase.
• Strong background in SW architecture and quality.
• Proficiency in developing simulation models for SoC.
• Advanced software development skills, including experience with scripting languages such as Python, C++.
• Deep understanding and experience with operating systems.
• Expertise in statistical data analysis and design of experiments.
• Familiarity with industry benchmarks, understanding the aspects of performance they measure, and conducting competitive analysis from previous generation products.

Experienced HireShift 1 (United States of America)US, Oregon, HillsboroUS, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

Key Responsibilities

• Architectural Leadership: Lead the architectural definition and integration of high-speed PHYs for client SoCs, including PCIe, CXL, USBx (e.g., eUSB2, USB3, USB4), Display, MIPI (D-PHY, C-PHY, M-PHY), Ethernet, and TSN. Collaborate with platform and product architects to analyze requirements and define critical performance, power, and area specifications to ensure the success of our products.
• IP Evaluation: Conduct technical evaluations of both internal and external PHY IPs, analyzing their performance characteristics against product requirements, and ensuring strategic alignment with overall product goals. Define detailed IP requirements, lead vendor engagement, and make strategic IP selection recommendations based on technical feasibility, cost-effectiveness, and long-term roadmap alignment.
• Technology Vision: Proactively research and evaluate emerging high-speed I/O technologies, industry trends, and evolving standards. Identify and champion opportunities to incorporate these advancements into our product roadmap, enhancing performance, power efficiency, and feature sets, and positioning our products for competitive advantage.
• Technical Documentation: Create clear and comprehensive architecture specifications and rigorous integration guidelines. Provide review and constructive feedback on related architectural specifications to ensure alignment with overall SoC goals.
• Technical Mentorship and Collaboration: Provide technical guidance and mentoring to junior engineers, fostering their growth and contributing to the overall team expertise. Champion a collaborative environment across multiple teams.
• Post-Silicon Leadership: Serve as a technical lead in the post-silicon debug and validation of high-speed I/O interfaces, leading taskforces and driving the resolution of complex issues. Oversee the validation process to ensure seamless and high-quality implementations.

Additional Skills:

• Demonstrated strategic acumen with proven effectiveness in collaborating with senior technologists and business leaders across organizational boundaries.• Demonstrated ability to network with and influence a broad range of stakeholders

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications:•

• BS degree in Electrical/Computer Engineering with a minimum of 15 years of experience.
• Master's or PhD degree in Electrical/Computer Engineering with minimum 12 years of experience
  

Preferred Qualifications:

• High familiarity with industry trends within the HSIO domain and the ability to map them to Intel roadmap/products and segment strategies.
• We look forward to welcoming a dynamic and innovative High-Speed I/O (PHY) Architect to our team. Apply now and be a part of shaping the future of our client SoC technology.
• Prior hands-on experience in High-Speed IO PHY Architecture and Design.
• Strong knowledge in the interoperability of HSIO PHYs within the PCIe, SATA, Ethernet, USB2, USB3, USB4, Display or MIPI IO Controller subsystems
• Strong technical leadership and communication skills

Experienced HireShift 1 (United States of America)US, California, FolsomUS, Arizona, Phoenix, US, California, Santa Clara, US, Oregon, Hillsboro
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

• Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing.

• Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.

• Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams.

• Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT.

• Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, low power synthesizable CPU.

• Optimizes CPU design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• Bachelors degree in Computer Engineering, Electrical Engineering or STEM related field with 3+ years of relevant work experience

• -OR- Masters degree in Computer Engineering, Electrical Engineering or STEM related field with 2+ years of relevant work experience

• -OR- PhD degree in Computer Engineering, Electrical Engineering or STEM related field

Relevant experience should include the following:

• Experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure

• PV convergence (including static timing and power analysis)

• Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks.

• Scripting in an interpreted language, minimum TCL in addition to at least one other (e.g. Perl, Python, Ruby)

• Demonstrated success in one or more of the following areas: Synthesis of a digital logic block, which was integrated into a large SoC or IP

Preferred Qualifications:

• 2+ years of industry experience/exposure with CPU Micro-Architecture

• Experience with Physical design best known practices concerning floor-planning, routing techniques, clock distribution

• Experience with of Static Timing Analysis, Noise analysis, and reliability verification techniques

• Experience with of RTL to GDS methodologies and formal equivalence

• Experience with Synopsys tool suite (Fusion compiler, ICC2, PrimeTime) or Cadence (genus/innovus)

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orschoolwork/classes/research.

Experienced HireShift 1 (United States of America)US, Oregon, Hillsboro
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

Your responsibilities may include but not be limited to:

• Define SoC fabrics, SoC hardware/software interface, and IP integration.

• Author high-level architecture specifications that meet product/market requirements and facilitate correct implementation by development teams

• Interact with Micro Architects, IP Architects, discrete GFX team, RTL Design teams, Verification teams, Emulation team, Power and Performance validation teams to understand the product requirements and define overall Display strategy to ensure the end product meets the PnP goals at pre-silicon estimation and post-silicon measurement.

• Interact withapplication/driver/firmware

The SOC Architect should possess the following attributes:

• Excellent written and verbal communication skills.

• Willingness to work effectively in a collaborative, cross-functional environment.

• Excellent problem-solving and debugging skills.

• Willingness to lead task forces to resolve problems.

Qualifications:

Bachelor's degree in Computer Science, Computer Engineering, or Electrical Engineering with:

• BS degree with 8+ years of industry experience

• OR- Master's degree with 6+ years of industry experience

• OR- PhD degree with 4+ years of industry experience

Candidate must have combined 4+ years of experience in the following areas:

• System-on-Chip (SoC) integration,

• SoC architecture,

• SoC design,

• System architecture ( such as Hardware / Software interface, PNP )

Preferred Qualifications:

• IP integration and SoC flows with IP's such as Graphics, Media, or Image Processing.

• Broad knowledge of computer systems (software, hardware, firmware, silicon).

• Experience with hardware/software interfaces.

• Power and Performance.

• Experience with at least one of the following: Memory controllers, cache hierarchy, fabrics, high speed I/O protocols.

Experienced HireShift 1 (United States of America)US, Oregon, HillsboroUS, California, Folsom, US, California, Santa Clara
Position of Trust

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

You Are

Responsibilities may include but are not limited to:

• As an FC Design Engineer, you will perform constraints management and STA verification.

• You will also be responsible for coordinating collateral handoffs between the FC Design team and other functions within back-end design such as Clocking, Power Delivery and Partition synthesis/APR.

• You will drive timing closure and provide collateral for SOC drops.

Behavior skills we are looking for:

• Excellent written and oral presentation skills, and willing to work across multiple organizations and geographies.

• Effective team player with continuous learning mindset.

• Strong analytical and problem-solving skills.

• Be willing to balance multiple tasks.

• Self-starter with a collaborative spirit, comfortable asking for help when needed

Qualifications:

You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• The candidate must have a Bachelor's Degree in Electrical Engineering, Computer Engineering or similar field with 4+ years of relevant experience

• -OR- MS degree in Electrical Engineering, Computer Engineering or similar field with 3+ years of relevant experience

• -OR- PhD in Electrical Engineering, Computer Engineering or similar field

Preferred Qualifications

• Experience with Static Timing Analysis (STA) using PrimeTime

• Experience with Scripting in one or more of the following languages (TCL, Perl, or Python)

• Experience with verification of power crossing ie. VC-static (VC LP), UPF

Experienced HireShift 1 (United States of America)US, Texas, AustinUS, Oregon, Hillsboro
Position of Trust

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

Responsibilities include:

• Develops complex code with C++ templates for optimal GPU kernels.
• Understand PyTorch or Similar framework’s usage of AI kernels and design the interfaces.
• Interacts with partner teams to understand the requirements and convert to tangible action items for development.
• Develop architectural documents for setting direction to larger team.

Behavioral traits that we are looking for:

• Excellent written and oral communication skills including technical details and concepts.
• Willingness to lead large teams of engineers with clear direction of complex requirements.
• Willingness adhering to specific timelines and delivering quality SW products.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orschoolwork/classes/research.

Minimum Qualifications:

• Bachelor’s degree and 6+ years or Master’s degree and 4+ years’ experience or Ph.D and 2+ years of experience in Computer Engineering, Computer Science, Data Science, Software Engineering, Electronic Engineering, Physics, Mathematics, Aerospace engineering, applied mathematics, mechanical engineering, or related technical disciplines.
• 3+ years of experience in complex C++ template-based development such as meta level programming.
• 2+ years’ experience with GPU architecture.
• 2+ years’ experience SYCL / CUDA knowledge.
• 1+ years’ experience with GEMM kernels.

How to stand out from other candidates (Preferred Qualifications):

• AI kernel developments (such as flash attention, MoE),
• Understanding of overall AI SW stack,
• Understanding of PyTorch architecture.

Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to

Experienced HireShift 1 (United States of America)US, Oregon, HillsboroUS, California, Santa Clara
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.