דרושים Foundry Web Application Architect ב-אינטל ב-ארהב

Job Description:

Since pioneering the world’s first hybrid silicon laser, IPS has led the industry in scalable, high-volumemanufacturing andadvanced photonics development. Our mission: deliver next-generation bandwidth growth with smaller form factors, co-packaging, and speeds from 400G today to 1.6T+ tomorrow.

We are seeking a Lead Analog SerDes Architect / Design Engineer to join our team and shape the future of data center connectivity. In this role, you will:

• Defining circuit architecture and enabling designs meeting power, and performance for next generation optical interconnects based on system specifications.
• As part of the team developing key integrated circuit components the engineer must be able to work collaboratively leading block level development.
• Specify, architect and design low voltage and low power Mixed-Signal integrated circuits and work collaboratively with digital designers.
• Plan design work with constraints on performance, schedule and quality.
• Provide guidance to junior designers and layout engineers.
• Guidance to develop test plans for post-silicon characterization.
• Document all design work with review materials and detailed design descriptions.

Minimum QualificationsThe ideal candidate should have a minimum of MS in Electrical Engineering with 8+ years of experience in high-speed serial links and deep knowledge of analog CMOS/BiCMOS designs in deep sub-micron process technologies.• Hands-on circuit design experience of SerDes blocks like Equalizers, PLL, Phase-Interpolators, CDR, etc. for 28Gbps+ data rates.
• Experience with design of inductors, transmission line, Trans-Impedance Amplifiers (TIA) and modulator drivers.
• Experience with design of precision analog circuits like ADC/DACs.
• Experience with designing PAM4/NRZ links.
• Experience with Mixed signal design flow
• Experience with full-chip designs, ESDs and verification flows.
Preferred Qualifications
• Familiarity with Optical communications.
• Experience with 400G/800G/1.6T optical links.
• Experience with package/test setup design.

Experienced HireShift 1 (United States of America)US, California, Santa Clara
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 214,730.00 USD - 303,140.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

We are seeking a Senior Device Engineer to drive the development of next-generation CMOS device technologies in our high-volume manufacturing environment. You will collaborate with cross-functional teams to develop innovative semiconductor solutions, optimize manufacturing processes, and deliver customized device architectures that meet our foundry customers' most demanding requirements.

Key Responsibilities

Data Analysis and Optimization: Utilize advanced data analysis, scripting, and analytical techniques to accelerate learning and drive continuous improvement. Interpret complex product data including inline, e-test, and SORT data to identify failure root causes and develop effective solutions.

Adaptability andProblem-Solving -Navigating changing technology landscapes while troubleshooting complex issues under tight timelines.

Qualifications:

Bachelor's Degree in Electrical Engineering, Physics, or related field with 7+ years of experience in CMOS device engineering, device physics, logic architecture, and interconnect development on leading-edge technology nodes.

The experience must include:

• Advanced CMOS device technology, preferably in a foundry environment.
• Foundry NPI. Device targeting and corner skew.
• IC wafer fabrication process engineering, manufacturing systems, semiconductor materials, and wafer testing across various fabrication areas including photolithography, advanced patterning, thin film deposition, planarization, defect metrology, and spectroscopy.
• Interpreting product data including inline, e-test, and SORT data, finding failure root cause and inline indicators, and driving for solutions.

Preferred Qualifications

• Post-graduate degree in Electrical Engineering, Physics, or related field with 6+ years of specialized CMOS device engineering experience.
• Direct hands-on experience in advanced node semiconductor technology development, particularly with 3nm-16nm FinFETs and sub-3nm GAA FETs.
• Experience in high-volume manufacturing environments with proven ability to balance foundry and customer needs.
• Expertise in Process Design Kit (PDK) silicon model target generation,silicon-to-simulationcorrelation, test structure design, device modeling, and electrical characterization.
• Direct customer-facing experience with familiarity in industry standards and certifications.

Experienced HireShift 1 (United States of America)US, Arizona, PhoenixUS, Oregon, Hillsboro
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 117,140.00 USD - 226,150.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

In this position, you will function as a senior technical member in the NPU architecture performance COE(center-of-excellence)

The role’s responsibilities include but are not limited to:

• Define performance model architecture and modeling flow to best reflect the interworking of NPU SW/HW.
• Implementing and testing performance models with systematic SW development practice.
• Conductperformance-and-poweranalysis of various neural network workloads.
• Utilize the performance data-driven flow to drive the NPU architecture definition.
• Collaborates with management, product owners, and project managers to evaluate feasibility of requirements and determine priorities for development.
• Performs pathfinding, surveys technologies, participates in standards committees, and presents at external and internal events.
• May interact with multiple technologists in the company to influence architectures and optimize/customize software offerings.

Qualifications:

You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Qualifications could be obtained through a combination of schoolwork, classes, research, and/or relevant previous job and/or internship experiences.

Minimum Qualifications

• Bachelor's Degree in Electrical Engineering, Computer Engineering, or Computer Science or related engineering field with 6+ years of relevant experience – OR – Master's Degree in Electrical Engineering, Computer Engineering, or Computer Science or related engineering field with 4+ years of relevant experience – OR – PhD in Electrical Engineering, Computer Engineering/Computer Science with 2+ years of relevant experience, or related engineering field
• 6+ years of experience in two or more of the following:
  • Knowledge of computer architecture concepts such as pipelining, caching, parallel computing with SIMD/VLIW,multi-core/multi-threading,data precision, memory hierarchy
  • Understanding HW modeling concepts such as event-driven, concurrency, etc.
  • Knowledge of AI framework, AI models and basic neural computing operations.
  • Knowledge of data precision, floating point vs fixed point computing trade-offs.

Preferred Qualifications

• Experiences for object-oriented programming in C/C++ or Python. Capable of design class objects, data structure and API methods are required.
• Prior usage of event-driven modeling language (SC/C++/Python) and platforms
• Prior experience in architecture definition and/or mentoring junior engineers is highly desirable.

Experienced HireShift 1 (United States of America)US, California, Santa ClaraUS, Arizona, Phoenix, US, California, Folsom, US, Oregon, Hillsboro, US, Oregon, Portland
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 168,100.00 USD - 299,040.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Responsibilities will include but are not limited to:

• Designing, implementing, growing, and maintaining Analysis Packages that are used by decision makers at Intel to improve product design, architecture, and manufacturing processes.
• Analysis Packages include a variety of techniques including mathematical optimization, simulation, and Machine Learning models.

You will work directly with our business partners to:

• Identify areas where applying analytics can improve business results.
• Research analytical techniques to address business problems.
• Design and implement analysis packages.
• Work with partners to ensure the analysis is adopted and used by the business.
• Measure the impact as time or cost savings and revenue increases for Intel.
• Research new techniques and propose new optimization tools for our applications.

In addition to the qualifications a successful candidate will demonstrate:

• Problem solver with the ability to generalize.
• Self-starter, organized, detail-oriented, and ability to move forward through ambiguity.
• Excellent written and verbal communication and presentation skills.

Minimum Qualifications:

The candidate must possess a PHD or master's degree inmathematics/Statistics/IndustrialEngineering/OperationsResearch/Computer Science, or STEM related field AND 4+ years of related experience in the following:

• Python, or other programming languages (Python preferred)
• Python analytical libraries (pandas, numpy, matplotlib, scikit-learn).
• Expertise deploying large scale Linear programming (LP) or Mixed Integer Programming (MIP) models

• Experience of statistical modeling, machine learning algorithms, causal inference and experimental design

Preferred Qualifications:

• Knowledge of advanced Numerical Optimization Concepts (Decomposition methods, Dynamic Programing, Stochastic Optimization, Robust Optimization).
• Demonstrated expertise with market segmentation, demand modeling and pricing models.
• Experience with source control (GIT, GitHub).
• Experience with test driven development and unit testing frameworks
• Working knowledge of Dev-OPS and/or ML-OPS
• Proven track record of solving complex business problems.
• Experience working effectively building and managing effective customer relationships.

• Comfortable with linear optimization software (ILOG/CPLEX, GUROBI, etc.)
• Experience with Meta-heuristics and non-linear optimization methods
• Experience handling structured and semi-structured datasets
• Ability to query analyze and present and visualize data.

Experienced HireShift 1 (United States of America)US, Arizona, PhoenixUS, California, Santa Clara, US, Oregon, Hillsboro
Position of Trust

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 160,570.00 USD - 226,690.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Role Overview:

The Senior Thermal Architect will lead thermal design and strategy for next-generation GPU, AI accelerators, and data center products. This role is critical to enabling high-performance computing at scale while meeting stringent thermal requirements. You will define thermal architecture across silicon, package, and platform levels, ensuring optimal thermal performance for products approaching multi-kilowatt levels:

Key Responsibilities:

• Define and deliver advanced packaging thermal solutions for advanced GPU/AI products
• Architect thermal strategies for 3DIC and advanced packaging technologies, including chiplets and heterogeneous integration.

• Develop analytical and experimental methods for thermal characterization and prediction.
• Drive co-optimization of thermal, electrical, and mechanical design across silicon, package, and system levels.

• Push the boundaries of thermal management to support Moore's Law progression.
• Evaluate and integrate emerging cooling technologies (e.g., liquid cooling, immersion cooling) for data center sustainability.

• Partner with silicon design, packaging, and platform teams to ensure thermal compliance and performance.
• Engage with external customers and ecosystem partners to align thermal solutions with product requirements.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Knowledge and/or experience listed below would be obtained through a combination of your school, work and/or classes and/or research and/or relevant previous job and/or internship experiences

Minimum Qualifications

• MS or PhD in Mechanical Engineering, Thermal Sciences, or related field.
• 10+ years in thermal design of semiconductor products
• Proven track record in thermal architecture and advanced packaging.
• Proficient in thermal simulation tools (e.g., CFD, FEA) and experimental validation.

Preferred Qualifications

• 10 + years experience in high-performance computing or data center products.
• Proven track record in GPU/AI thermal architecture and advanced packaging.
• Experience with rack-scale cooling solutions and liquid cooling technologies.
• Familiarity with AI/GPU performance trends and their thermal implications.
• Strong understanding of power delivery, energy efficiency, and cooling technologies.
• Ability to influence architecture decisions and drive innovation across global teams.

Experienced HireShift 1 (United States of America)US, Arizona, PhoenixUS, Oregon, Hillsboro
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 136,990.00 USD - 262,680.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

What Intel offers:

• We give you opportunities to transform technology and create a better future, by delivering products that touch the lives of every person on earth.
• As a global leader in innovation and new technology, we foster a collaborative, supportive, and exciting environment where the brightest minds in the world come together to achieve exceptional results.
• We offer a competitive salary and financial benefits such as bonuses, life and disability insurance, opportunities to buy Intel stock at a discounted rate, and Intel stock awards (eligibility at the discretion of Intel Corporation).

As a Software Application Development Engineer, you will:

Design, develop, test, and debug software applications used by end users or integrated with other applications by ISVs (Independent Software Vendors). Development may span the full application stack, including frontend and backend application development.

Use modern software development methodologies and programming languages.

Follows secure coding practices and software legal compliance guidelines.

Analyze user stories, write functional and test code, automate build and deployment, and perform unit integration and end-to-end testing of applications.

Complete SDL tasks with the assistance of product security engineers and provide input to technical writers to complete product documentation and procedures for installation and maintenance.

May also interact with end users to define system requirements and/or necessary modifications.

Applicants should possess the behavioral traits below:

Demonstrated data analytics skills to communicate complex data in a simple, actionable way.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are a plus factor in identifying top candidates.Experience listed below would be obtained through a combination of yourschoolwork/classes/researchand/or relevant previous job and/or internship experiences.

What we need to see (Minimum Qualifications):

• US Citizenship Required.
• Ability to obtain and maintain active US Government Security Clearance.
• Bachelor's degree in computer science, computer engineering, electrical engineering, or a similar field and 6+ years' is relevant experience OR a master’s degree in computer science, computer engineering, electrical engineering, or a similar field and 3+ years' relevant experience.
• Proven Engineering Excellence: 4+ years of professional software development experience with deep expertise in both dynamically-typed languages (Python, JavaScript, etc.) and statically-typed languages (Java, C++, etc.), with a track record of delivering high-impact solutions
• Advanced Technical Mastery: Expert-level (4+ years’ experience) with data structures and algorithms, with the ability to architect optimal solutions using complex data structures (trees, graphs, hash maps ) and make informed trade-offs between performance, memory usage, and maintainability.
• Design Leadership: (4+ years'experience). withsoftware design patterns and architectural principles, with proven ability to design scalable systems, lead technical decision-making, and establish coding standards that solve complex business challenges at scale
• Collaborative Technical Excellence: 2+ years’ experience sharing knowledge and best practices with team members through code reviews, pair programming, and technical discussions. You enjoy helping colleagues grow while maintaining focus on your own technical deliverables and project contributions.

Preferred Qualifications:

• Master degree in computer science or a related field and 8+ years' experience.
• Semiconductor Fabrication and Lithography.
• Knowledge of EDA (Electronic Design Automation) tools.
• Database Concepts, SQL and hardware platform architecture, networking.
• Distributed computing and/or multi-threading experience.
• Information Security protocols.
• Experience with full-stack web development.

Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion.

Experienced HireShift 1 (United States of America)US, California, Santa Clara
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 132,810.00 USD - 258,410.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Key Responsibilities:

• Lead the co-design of silicon and package, focusing on DDR PHY and mixed signal IP integration for server SOCs.
• Design bump maps, floor plans, and manage area constraints for PHYs, collaborating closely with packaging technical experts.
• Conduct hands-onpackage extractionsand simulations(signal integrity, power integrity)
• Finalize bump-out, floor plan, and area decisions at the end of tech readiness phases.
• Interface with packaging teams on advanced technologies (e.g., C4 bumps, micro bumps, EMIB, hybrid bonding as needed).
• Focus on design, development, and architecture, not process or materials engineering.

Required Experience:

• Experience in both silicon design (preferably mixed signal/analog) and packaging co-design.
• Background in DDR, SOC, or similar high-speed interface development.
• Hands-on expertise with bump mapping, floor planning, and packaging constraints.
• Proven ability to collaborate across silicon and packaging teams, including risk assessment and simulation.
• Familiarity with advanced packaging technologies (hybrid bonding, EMIB, etc.) is a plus but not required.
• Individual contributor or principal engineer level preferred; management experience is not required.
• Experience at leading companies in advanced packaging and PHY design (e.g., Apple, Broadcom, Qualcomm, Micron, AMD, Nvidia).

Qualifications:

• Bachelors in electrical engineering, chemical engineering, mechanical engineering, material science or similar field (Master’s or Ph.D. preferred).
• 10+ years in silicon and packaging co-design

Experienced HireShift 1 (United States of America)US, California, FolsomUS, Arizona, Phoenix, US, California, Santa Clara, US, Oregon, Hillsboro
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: