דרושים ב-Intel ב-Ireland

Intel has significant employee locations in EMEA, with major operations inand
Israel:

• Ireland: Large semiconductor manufacturing campus in Leixlip

• Israel: Multiple research and development centers in Haifa, Petah Tikva, and Jerusalem

.

Core Responsibilities:

• Provide expert advice on all global employment tax matters, including payroll, benefits and equity, expatriate and globally mobile employee taxation.

• Supervise aspects of employment tax compliance and oversee employment tax-related submissions, including advisory support with payroll tax and social security audits.

• Identify, monitor, and mitigate employment tax risks and legislative change across the EMEA region by developing and implementing robust governance frameworks whilst identifying opportunities for standardization and simplification.

  • Includes international tax developments like OECD initiatives and communicating their potential impact on business stakeholders.

• Act as a key liaison between the tax department and other internal teams, including HR, Payroll, Legal, and Finance.

  • This role also works closely with external tax advisors.

• Assist with global mobility and tax equalization policy and process design, compensation and benefits programs, business initiatives, and reorganizations to ensure they are tax-efficient and compliant across various EMEA jurisdictions.

Previous experience:

• Public accounting or a related field, with a focus on tax compliance and consulting, is required.

• In-depth understanding of national and local income tax and social security tax laws for the EMEA region, as well as employer payroll reporting and withholding requirements.

• Ability to analyze complex financial data and tax regulations to identify potential risks and innovative solutions.

Communication:

• Excellent communication skills for explaining complex tax issues to various internal and external stakeholders and all employee grade levels, including senior executives.

• Diplomatic and collaborative skills to build strong relationships with stakeholders and tax authorities across different jurisdictions.

Minimum Qualifications:

6 or more years of relevant experience focused on mobility and employment tax from a combination of a large public accounting firm or large corporate experience

Key Responsibilities

• Execute all stages of the physical design flow, including:

• Synthesis

• Floorplanning

• Place and Route (P&R)

• Clock Tree Synthesis (CTS)

• Routing

• Static Timing Analysis (STA)

• Power and clock distribution

• Reliability and noise analysis

• Perform verification and signoff tasks such as:

• Formal equivalence verification

• Static and dynamic power integrity checks

• Layout verification

• Electrical Rule Checking (ERC)

• Analyze design results and recommend fixes for violations to support current and future product architectures.

• Optimize designs for power, performance, and area (PPA).

• Contribute to the development and automation of physical design methodologies and flows.

Required Skills & Experience

• Low power design techniques

• Physical/structural design flow

• Timing constraints

• Timing closure and physical clock design

• Proficiency with industry-standard EDA tools

• Bachelor’s (NFQ 8) or Master’s( NFQ 9)degree in Engineering or equivalent

In this position, you will become a member of the digital design team delivering next-generation NPUs for AI PCs. As part of this high-performance team, you will be involved in the digital design of super efficient, low power IP to run the latest AI models. The team is looking to hire an engineer with an interest in RTL development and in artificial intelligence.

Your responsibilities will include:

• Developing the micro-architectural specification of complex design block(s).
• Logic implementation of complex design block(s) using RTL coding techniques.
• Working with pre-Silicon validation engineers to develop cluster-level directed/random tests and environments.
• Working with the Physical Design (Layout) team on Synthesis, Formal Verification, and Timing Convergence.
• Interacting closely with other teams such as Architecture, DFx, Software, Firmware, and Post-Silicon Validation.

Required Experience:

• Exposure to RTL level Digital Design using System Verilog and/or Verilog.
• Proven track record of successful delivery of projects.
• A self-starter with the ability to manage your own time effectively and clearly communicate your ideas.
• Ability to work well in a diverse team environment.

• ExperienceinASIC, SoC, or FPGA design experience.
• Experience with industry-standard development tools and methodologies.
• Experience with languages such as C and/or C++, SystemC, OVM/UVM, SVAs, Perl, Shell scripting.
• Experience in some of the following areas/tools: Synthesis, Formal Verification, DFT, VCS, PrimeTime, Design Compiler, Jasper (FPV).
• Understanding topics such as model quantization, emerging data types etc., and their usage in inference for CNNs, LLMs and other deep learning models.

Responsibilities / What You'll Do

• Responsible for safety, quality, operational performance, and improving productivity in addition to cost reduction for their module.

• Ownership and qualification of process modules and/or equipment, including Preventative Maintenance, Root Cause analysis, Monitoring Process Performance, and Defect Reduction

• Collaborate with cross-functional teams to solve technical challenges using structured, model-based problem-solving techniques.

• Contribute to sustaining and improving Intel's Virtual Factory standards and process matching across global sites.

• Engage in continuous learning and development through mentorship and training.

MinimumRequirements:

• Currently pursuing a Level 8 or Level 9 qualification in a relevant STEM discipline (e.g. Physics, Applied Chemistry, Chemical Engineering, Electronic Engineering, Mechanical Engineering,Electrical and Mechatronic Engineeringetc.).

• Strong analytical and problem-solving skills.

• Excellent communication skills - both written and verbal.

• Ability to work independently and as part of a diverse, high-performing team.

• Willingness to work in a cleanroom environment.

• Strong attention to detail and disciplined approach to procedures.

PreferredExperience:

• Experience with data analysis tools and software (e.g. JMP, Python, Excel).

• Ability to summarize data for technical and non-technical audiences.

What We Offer

• A dynamic, inclusive, and innovative work environment.

• Hands-on experience with cutting-edge semiconductor technology.

• Mentorship from experienced engineers and opportunities to grow your technical and professional skills.

• Exposure to Intel's global manufacturing operations and Virtual Factory model.

• The chance to contribute to meaningful projects that impact the lives of every person on the planet.

Intel NPU group specializes in design of high-performance, ultra-low power Neural network IP technology for advanced AI applications. Step inside our world and you'll find one brilliant mind after another working together in a spirit of collaboration that is simply contagious. And through this shared dedication, a culture of innovation and exploration, we do more than deliver the latest technologies. We deliver the future. And this is where you come in. We need innovators and proven communicators like you to push our thinking. We need your strong collaboration and organizational skills, as well as your ability to effectively work with and manage teams. You will help push us to the next level.

R&D Engineering Roles:

Hardware Focused Roles:

• Physical design team - Physical layout, design and verification.
• RTL Design team - Hardware IP design and verification.
• Architecture team - Hardware Architecture design.
• Verification team - Hardware IP verification and design qualification.
• AI Applications team - Evaluate Neural network use cases Software focused roles.

Software Focused Roles:

• Complier team - Developing an optimized compiler toolchain for the IP to deliver inference performance though the OpenVino tool kit (Intel Distribution of OpenVINO Toolkit).
• NPU Software - Developing software drivers and firmware for the IP.
• Pre-Silicon Simulation team - IP Models and integrating them into virtual platforms.
• DevOps - IT and Operational services.

Mixed SW/HW Roles:

• Emulation team - Developing and validate pre silicon models on FPGA and emulation platforms.
• Design Automation - Infrastructure and automation.

Lab & Remote Operations Focused Roles

• Supporting our FGPA emulation, remote testing and development farms.
• Testing and validation of product specifications and characteristics.
• Use case projects including demo development, utilizing our extensive prototyping hardware.
• Development of lab tools and services.
• This role comprises significant operational management and business management elements in areas such as:
• EHS (Environmental Health and Safety), logistics and controlled technology, privacy (GDPR), operational management and finance.
• Successful lab support engineers will develop advanced communication and organizational skills to manage the dynamic, fast changing lab environment.
• You will also gain a great broad understanding of all aspects of our technology development, across our cutting-edge product portfolio.
• Graduate/Technical Graduate position as appropriate.

Required Competencies

• Strong analytical and problem-solving skills.
• Self-motivated with ability to work independently and manage stakeholders.
• Excellent written and verbal communication skills.
• Demonstrated team dynamics / ability to work as part of a high performing team.
• Ability to deal with ambiguity in defining activities and direction.
• Good planning and organization skills.

In this position, you will be a member of the silicon engineering division of the NEX Group. As part of this high-performance team, you will be involved in the digital design of leading-edge Cryptographic, Ethernet, and Packet Processing solutions on best-in-class Ethernet products. The team is looking to hire engineers with RTL development experience to augment and provide technical leadership within the existing team. Experience in adjacent engineering disciplines such as software development would also be considered.Responsibilities:

• Developing the micro-architectural specification of complex design block(s).

• Logic implementation of complex design block(s) using RTL coding techniques.

• Working with pre-Silicon validation engineers to develop cluster-level directed/random tests and environments.

• Working with the Physical Design (Layout) team on Synthesis, Formal Verification, and Timing Convergence.

• Interacting closely with other teams such as Architecture, DFx, Software, Firmware, and Post-Silicon Validation.

Educational Qualifications:

• At minimum, an Honours degree (level 8 on www.nfq.ie) in Electronic Engineering, Computer Science, or equivalent.

Required Experience:

• 6+ years of RTL level Digital IC Design experience using System Verilog and/or Verilog.

• Strong ASIC, SoC, or FPGA design experience.

• Proven track record of successful first-time delivery of projects.

• A self-starter with the ability to assume leadership roles.

• Ability to work well in a diverse team environment.

• Experience with industry-standard development tools and methodologies.

Preferred Experience:

• Experience with languages such as C and/or C++, SystemC, OVM/UVM, SVAs, Perl, Shell scripting.

• Experience in some of the following areas/tools: Synthesis, Formal Verification, DFT, VCS, PrimeTime, Design Compiler, Jasper (FPV).

Responsibilities:

• Conduct workload analysis and performance debugging to identify bottlenecks and drive resolution through hardware and/or software fixes.
• Evaluate AI-GPU hardware architecture and influence the product roadmap through a deep understanding of AI algorithms, customer needs, and software frameworks.
• Develop and enhance internal performance analysis tools.
• Develop highly optimized GPU kernels and software stacks, collaborating with partner teams to deliver high-performance solutions.
• Provide a comprehensive view of solutions and support both pre- and post-silicon activities.
• Collaborate with experts to analyse next-generation requirements and guide research and academic partnerships.

Minimum Qualifications:

• MS in Computer Engineering, Computer Science, Electrical Engineering, or Mathematics.
• 2-3 years of experience in GPU/CPU architecture for AI workloads.
• Proficient in Python, C/C++.Good data analysis and presentation skills.

Preferred Qualifications:

• Knowledge of AI and deep learning, including Large Language Models (LLM) and Stable Diffusion.
• Experience in performance analysis/performance debugging.
• Experience in building analytical and/or simulation-based performance models.
• Knowledge/experience in CPU, GPU, or memory design/architecture, and/ormicroarchitecture/RTL/design/processtechnologies.
• An aptitude to learn new things quickly in this fast-changing domain and flexibility to work on any mix of the above roles as needed.

This role is ideal for candidates who are eager to learn about AI hardware, possess strong collaboration skills, and can thrive in a fast-paced hardware/software development environment. Requirements listed would be obtained through a combination of industry-relevant job experience, internship experiences, and/orschoolwork/classes/research.