דרושים ב-Broadcom ב-United States, Chandler

Broadcom Central Engineering is looking for an engineer to help with the development, installation, and testing of silicon verification decks, primarily Calibre, in support of advanced FINFET and GAA technologies. Experience with Calibre and Virtuoso is essential as the position will require development of test designs. Strong programming skills in PERL, TCL, SKILL and UNIX shell languages will also be necessary as the individual will be responsible for extending or possibly replacing an existing infrastructure for regression testing, currently written in PERL. Familiarity with circuit extraction and simulation would be helpful to extend regression testing also to cover extraction tool support, primarily StarRC and HSPICE, although QRC and SPECTRE familiarity is also desirable.

Knowledge of industry EDA tool availability and capabilities in these areas is expected.

Responsibilities:

The candidate's general responsibilities include the following:

• Development and deployment of Calibre decks for advanced FINFET/GAA nodes.

• Definition of tool acceptance and certification criteria in partnership with Broadcom teams, Foundry and EDA vendors to meet high-performance IP design needs.

• Definition and development of IP test-cases and basic test-structures to validate tools and technology related updates on predictable schedules.

• Development of software for automation in Skill, PERL, UNIX shell scripting and tool-flow integration.

• Creation of documentation and hands-on training for AMS Design & Layout engineers as needed.

• Tracking and resolution of tool and technology file issues with hands-on management per objectives of Foundry and EDA vendor support teams.

• Monitoring of EDA industry trends and new capabilities by attending conferences and research forums. Engagement with EDA and Foundry R&D teams on advanced node capability roadmaps, identification of new tools, development of evaluation criteria and processes and then serving as champion for introduction and usage within the Broadcom design community.

Requirements:

• Masters in Electrical Engineering or Computer Science plus 10+ years of EDA experience.

• User level familiarity with related CAD Tools: Calibre, Virtuoso Layout & Schematics, QuantusQRC/StarRC/QuickCap/Raphael,and simulation using SPECTRE/HSPICE.

• Solid background in programming skills, basic layout design, and technology knowledge to help solve layout, physical verification, and post-layout extraction challenges and problems.

• Experience in all phases of CAD tools from evaluation, QA, test, release, and user support to documentation

• Expertise in Cadence Skill, PERL, UNIX sShell and utilities

• Excellent interpersonal, communication, and presentation skills, along with strong multi-tasking skills, attention to detail, and the ability to work well in a team

The annual base salary range for this position is $127,100 - $203,400This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Job Responsibilities

• Automation of standard cell design checks and flows

• Develop and maintain CAD flows

• Interface with CAD and PDK techfile teams to understand requirements and identify opportunities for custom checks and flow updates

Key Requirements

• Experience with Virtuoso, Cadence Skill programming, Calibre/ICV preferred

• Experience with scripting using Unix, Perl, TCL or Python

• Prior experience with large datasets, ML, high volume data analysis

• Understanding of analog or standard cell library flows

• Understanding of .lib data

• Digital or mixed-signal circuit design knowledge

• Familiarity with EDA tools used for cell design, layout, verification, simulation and characterization

Qualifications & Experience

Bachelor's in Electrical or Computer Engineering and 8+ years of related experience required

Additional Qualifications

• Excellent written and verbal communication skills

• Collaborate and work within and across teams

• Lead major initiatives to completion with minimal supervision

Compensation and Benefits

The annual base salary range for this position is $107,000 - $171,000

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Job Responsibilities

• Design standard or custom digital logic and sequential cells or macros at the transistor level

• Make design tradeoffs for PPA, DTCO optimization

• Simulate and analyze circuit designs using industry standard simulation tools

• Develop and maintain CAD flows

• Interface with design teams to understand requirements and identify opportunities for custom solutions

Key Requirements

• Digital or mixed-signal circuit design knowledge

• Understanding of cell layout or physical design

• Familiarity with FinFet and RibbonFet / GAA Process Technology nodes

• Familiarity with EDA tools used for cell design, layout, verification, simulation and characterization

• Experience with Virtuoso, Cadence Skill programming preferred

• Experience with scripting using Unix, Perl, TCL or Python

Qualifications & Experience

Bachelor's in Electrical or Computer Engineering and 8+ years of related experience required

Additional Qualifications

• Excellent written and verbal communication skills

• Collaborate and work within and across teams

• Lead major initiatives to completion with minimal supervision

Compensation and Benefits

The annual base salary range for this position is $107,000 - $171,000

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Job Responsibilities

• Design standard or custom digital logic and sequential cells or macros at the transistor level

• Make design tradeoffs for PPA, DTCO optimization

• Simulate and analyze circuit designs using industry standard simulation tools

• Develop and maintain CAD flows

• Interface with design teams to understand requirements and identify opportunities for custom solutions

Key Requirements

• Digital or mixed-signal circuit design knowledge

• Understanding of cell layout or physical design

• Familiarity with FinFet and RibbonFet / GAA Process Technology nodes

• Familiarity with EDA tools used for cell design, layout, verification, simulation and characterization

• Experience with Virtuoso, Cadence Skill programming preferred

• Experience with scripting using Unix, Perl, TCL or Python

Qualifications & Experience

Bachelor's in Electrical or Computer Engineering and 12+ years of related experience required

Additional Qualifications

• Excellent written and verbal communication skills

• Collaborate and work within and across teams

• Lead major initiatives to completion with minimal supervision

Compensation and Benefits

The annual base salary range for this position is $127,000 - $203,000

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.