דרושים Commercial Product Operations Lead ב-Arm ב-United States, San Jose

As part of the methodology team, you will lead the development, improvement, and deployment of low power structural check methodologies across multiple SoC and IP projects. This role involves designing automated flows for UPF/CPF consistency, power domain integrity, and structural rule validation at both RTL and netlist levels. You will collaborate closely with design, verification, and EDA partners to ensure robust, scalable, and high-coverage power-aware design signoff strategies across technology nodes and product segments.

• Develop and maintain low-power structural check methodologies (UPF/CPF validation, isolation, level shifters, retention, domain crossings).
• Build automated flows using tools like Synopsys VC LP, SpyGlass-LP, and Conformal LP.
• Ensure power intent consistency and early issue detection through collaboration with design and verification teams.
• Integrate structural checks into signoff regressions with high coverage and low false positives.
• Work with vendors and internal teams to enhance tools, debug issues, and improve efficiency.
• Drive global adoption through documentation, training, and support.
• Assist in audits, quality reviews, and milestone checks.

• 5+ years of Strong background in low-power structural methodologies and UPF/CPF-based flows.
• Deep understanding of power intent specs, domain partitioning, isolation, and retention.
• Hands-on experience with tools like VC LP, SpyGlass-LP, or Cadence CLP.
• Skilled in scripting (Python, Perl, TCL) for flow automation.
• Experience with large SoC/IP designs across advanced nodes.
• Confirmed ability to debug structural issues and drive closure.
• Strong communication and documentation skills.

• Experience with formal verification or functional simulation for power-aware designs.
• Knowledge of complex power analysis and correlation with structural checks.
• Exposure to hierarchical low-power signoff strategies in multi-voltage or multi-power domain SoCs.
• Familiarity with power-aware DFT, scan strategies, and low-power aware synthesis flows.
• Participation in industry working groups (e.g., Accellera UPF), technical conferences, or publications.
• Involvement in tool benchmarking, vendor collaborations, and internal tool qualification projects.

We are proud to have a set of behaviors that reflects who we are and guides our decisions, defining how we work together to surpass ordinary and shape outstanding!

• Partner and dedication towards or customers
• Collaborate and communication
• Originality and resourcefulness
• Team and personal development
• Impact and influence
• Deliver on your promises

As a member/lead of SOC emulation team you will be involved in:

• Supporting multiple Emulation environments using the latest emulation techniques.
• Building early SoC platforms to facilitate performance/power analysis and debug. Able to handle/modify RTL and stitch together SoCs with standardized interfaces from scratch for bare-metal and validation OS based bringups. Collaboration with design teams to ensure the production of clean RTL code.
• Developing system level testbenches to implement performance and power benchmarks, simpoints and use cases in emulation platform. Integrate observation options to assemble and debug performance/power studies, correlate with pre-Si simulation/post-Si, lead larger implementation teams for emulation at later implementation phases and work with post-Si teams for analysis/tuning. Help drive innovation in model building and debugging methodologies.
• Collaborate with SoC Architecture team to create testplans covering all performance and power metrics for the product. Define flexible/reduced SoC configurations allowing reduction in simulation and emulation capacities, while providing accurate performance estimates. Collaborate with emulation vendors to define distributed systems to split huge SOC netlist between multiple emulation boxes.

• Experience (+10 years) in SoC Performance verification and emulation environment bringup in the semiconductor industry.
• A background in Electrical Engineering, Computer Engineering, or Computer Science with an expertise in computer architecture and microarchitecture.
• Proficient in RTL (SystemVerilog, Verilog, VHDL), C/C++ for bare metal code, system validation using OS, test code development, strong scripting capabilities, particularly in Python, TCL, and shell scripting.
• Excellent communication, and interpersonal skills with ability to convey effectively complicated solutions.
• Drive early and detailed performance/power analysis as an experienced Emulation Architect at Arm, focusing on diverse silicon platforms

• Experience in developing, building, and releasing large multi-billion gate hardware emulation models. In-depth knowledge of key hardware emulation vendor solutions for emulation and prototyping.
• Experience working with design and software teams on design verification tests, PPA workloads, and software workloads.

We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to surpass ordinary and shape outstanding!

• Partner and customer focus
• Collaboration and communication
• Creativity and innovation
• Team and personal development
• Impact and influence
• Deliver on your promises

As a member/lead of SOC emulation team you will be involved in:

• Supporting multiple Emulation environments using the latest emulation techniques.
• Building early SoC platforms to facilitate performance/power analysis and debug. Able to handle/modify RTL and stitch together SoCs with standardized interfaces from scratch for bare-metal and validation OS based bringups. Collaboration with design teams to ensure the production of clean RTL code.
• Developing system level testbenches to implement performance and power benchmarks, simpoints and use cases in emulation platform. Integrate observation options to assemble and debug performance/power studies, correlate with pre-Si simulation/post-Si, lead larger implementation teams for emulation at later implementation phases and work with post-Si teams for analysis/tuning. Help drive innovation in model building and debugging methodologies.
• Collaborate with SoC Architecture team to create testplans covering all performance and power metrics for the product. Define flexible/reduced SoC configurations allowing reduction in simulation and emulation capacities, while providing accurate performance estimates. Collaborate with emulation vendors to define distributed systems to split huge SOC netlist between multiple emulation boxes.

• Experience (+10 years) in SoC Performance verification and emulation environment bringup in the semiconductor industry.
• A background in Electrical Engineering, Computer Engineering, or Computer Science with an expertise in computer architecture and microarchitecture.
• Proficient in RTL (SystemVerilog, Verilog, VHDL), C/C++ for bare metal code, system validation using OS, test code development, strong scripting capabilities, particularly in Python, TCL, and shell scripting.
• Excellent communication, and interpersonal skills with ability to convey effectively complicated solutions.
• Drive early and detailed performance/power analysis as an experienced Emulation Architect at Arm, focusing on diverse silicon platforms

• Experience in developing, building, and releasing large multi-billion gate hardware emulation models. In-depth knowledge of key hardware emulation vendor solutions for emulation and prototyping.
• Experience working with design and software teams on design verification tests, PPA workloads, and software workloads.

We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to surpass ordinary and shape outstanding!

• Partner and customer focus
• Collaboration and communication
• Creativity and innovation
• Team and personal development
• Impact and influence
• Deliver on your promises