דרושים ב-Arm ב-United States, San Diego

• As a creative design engineer with a knowledge of subsystems and SoCs you will be part of a team developing the logic for our reconfigurable Fuse Subsystem.
• Work as part of the design team to understand the Fuse Subsystem requirements, and develop the design specifications which meet the quality, reliability, manufacturing and reconfigurable needs across multiple SoC's.
• Your key responsibilities will include crafting design micro-architecture specifications, developing the RTL, fixing bugs, running design checks and contributing to the generation of implementation constraints.
• Work closely with the verification team to review test plans and help debug design issues in addition to crafting UVM components for IP and SoC integration of the Fuse Subsystem
• As part of the design team, you will contribute to developing and enhancing the design methodologies used by the team
• Mentor and support other members of the team to enable the successful completion of project activities
• Required to work with Project Management to define plans and schedules

In addition to bringing your accomplishment of either Bachelors or Master’s degree in Computer Science or Electrical/Computer Engineering or a similar related field and 5+ years' experience working in design of complex subsystems or SoCs, you will need:

• Experience in digital hardware design for complex systems using System Verilog.
• Experience with working with analog hard IP integration, timing diagrams, BMODs
• Experience with reconfigurable IP / Subsystem design
• Experience with power and clock domain crossing
• Experience with static design checks like linting, CDC/RDC, X-propagation
• Exposure to all stages of design: initial concept, specification, implementation, testing, documentation and support
• Experience collaborating with the verification team on design quality closure
• Experience with Perl, Python or other scripting language
• Leadership, mentoring or coaching experience

• Experience with ARM-based designs and/or ARM System Architectures
• Experience with verification methodologies – UVM
• Experience with UPF, IP-XACT
• Experience leading teams or projects
• Experience developing and integrating subsystems for PCIe, UCIe, DDR/LPDDR/HBM, Ethernet etc.
• Understanding of DFT topics: RTL testability, scan insertion, OCC

We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together. These behaviors are assessed as part of the hiring process:

• Partner and customer focus
• Collaboration and communication
• Creativity and innovation
• Team and personal development
• Impact and influence
• Deliver on your promises

We offer a hybrid approach to home and office working to provide an adaptable experience for all employees. We expect some working time to be spent in office, to promote a strong collaborative environment with good team integration but are accommodating to different home working requirements.

Design engineers in the GPU Group are responsible for the development of next-generation GPU IP for graphics and compute. They are required to have in-depth understanding across all the elements that contribute to the products’ successful delivery, including: low-power design techniques, awareness of the impact of design decisions on system performance, ability to produce designs that are area efficient, and the verification techniques that are employed to ensure high-quality robust designs.

We are looking for dedicated, hard-working engineers who are capable of owning parts of GPU micro-architecture, contributing to all phases of the design flow:

• The definition and implementation of hardware designs
• Technically supporting other specialists
• Writing and reviewing design and verification documentation
• Planning and tracking design tasks to meet the targets at the planned time

• Hands-on experience using System Verilog, Verilog or VHDL HDL for design
• Experience in complex designs that achieve performance, area, frequency and power targets
• Ability to make judgements on functionality, performance, and physical implementation trade-offs
• Experience of producing specifications and documentation describing complex designs
• Ability to own all stages of a project from start to completion: concept, specification, implementation and testing, support

• Practical experience of working on GPU/microprocessor designs
• Knowledge of 3d Graphics - OpenGL, Vulkan, DirectX
• Working knowledge of SystemVerilog Assertions (SVA)
• Knowledge of scripting eg Python, Perl or UNIX shell scripting

At Arm, the SoC Interconnect Architect defines and designs innovative on-chip interconnect architectures-coherent and non-coherent-for scalable SoC platforms. You will work across markets including mobile, automotive, datacenter, networking, and IoT, contributing to production-quality silicon with top-tier performance and efficiency. Collaborating with multi-functional teams, you'll shape the interconnect infrastructure that powers next-generation SoCs.

• Architect on-chip interconnect solutions (coherent and non-coherent) across a range of silicon products.
• Collaborate with performance, power, and physical design teams to optimize interconnect fabrics.
• Develop SoC architecture using Arm product IP to meet compute performance targets.
• Define interconnect platform roadmaps in partnership with core technology teams.
• Optimize end-to-end platform solutions with software and hardware teams.
• Guide early architecture discussions with customers and partners, delivering ready-to-implement specifications.
• Support use case analysis and performance analysis.
• Drive innovation and continuous improvement in interconnect technologies.

• 8+ years' experience in on-chip interconnect architecture for various silicon products.
• 8+ years' experience with coherency protocols and hierarchical cache design.
• Proven track record working with performance, power, and physical design teams on interconnect solutions.
• Experience designing scalable SoCs across multiple sectors and process nodes.
• Knowledge in areas such as heterogeneous compute, PCIe/CXL, security, caching, memory systems, and packaging.
• Strong communication and leadership skills with executive-level influence.
• Bachelor's or Master's degree or equivalent experience in Electrical or Computer Engineering and 10+ years in semiconductor roles.

• Ability to thrive in dynamic environments with shifting priorities.
• Constructive, strategic mindset to challenge and improve status quo.
• Track record of delivering complex projects on time and to spec.

Arm is proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work collaboratively to defy ordinary and shape extraordinary!

• Partner and Customer Focus
• Collaboration and Communication
• Creativity and Innovation
• Team and Personal Development
• Impact and Influence
• Deliver on Your Promises

We work on software development methodologies, educational content, example software, and development tools. Our top priority is to ensure that software developers successfully adopt Arm technology. You will engage with developers, understand their needs, and map out either existing tool solutions or prototype new solutions that would help them achieve their project goals. You will also partner with other team members to create new tools and software to support adoption and deployment of Arm technology. We work across a variety of computing segments, including servers and cloud, mobile, laptops, and embedded systems. As part of a small and dynamic team, you will pick up a variety of engineering, support, and technical marketing tasks. The most important requirement is that you have the drive and willingness to learn and are as passionate about new technology as we are!

• Work alongside customers and partners to support, train and assist them in their use of Arm technology, sharing knowledge and working side-by-side to ensure their success
• Make Arm products better by playing the role of the user and providing feedback to product development teams
• Contribute to the Arm Learning Paths at https://learn.arm.com as a content creator and technical reviewer
• Assist in the creation of other technical marketing material such as conference talks, case studies, blogs, videos, and demos

• Bachelors (BS) or Masters (MS/MSc) in Electronics, Electrical, or Computer engineering or equivalent practical experience
• Familiarity with the Arm architecture and programming experience in Python or C++
• Creativity and ability to communicate ideas effectively, and self-motivated with strong interpersonal/collaboration skills
• Familiarly with cloud service providers, including Amazon Web Services (AWS), Microsoft Azure, and Google Cloud Platform (GCP)
• Comfortable with software development on Linux

• Ability to work in a geographically diverse and distributed team
• Genuine curiosity about new technology and solving developer problems
• Practical embedded system and microcontroller experience

• Lead electrical engineering efforts from conceptual studies through design, construction, commissioning, and operation.
• Develop and review electrical design standards and specifications, ensuring alignment with industry standard processes and Arm’s reliability goals.
• Perform detailed engineering analysis (load flow, short-circuit, and arc flash studies).
• Provide direction, coordinate with, and review the designs of external consultants and partners.
• Conduct site inspections and factory acceptance tests (FATs) for critical power infrastructure UPS, switchgear, generators, PDUs, etc.
• Provide guidance on power distribution, grounding, redundancy (N, N+1, 2N), and energy efficient strategies.
• Support operational readiness, maintenance planning, and root-cause analysis of electrical issues impacting uptime.

• Bachelor’s or Master’s degree or equivalent experience in Electrical Engineering.
• Deep technical knowledge of medium and low voltage power systems, power distribution, UPS systems, generators, battery energy storage systems (BESS), power distribution units (PDUs), and other related electrical infrastructure found within data center environments
• Proficiency with electrical modeling tools (SKM Power Tools and ETAP)
• Strong familiarity with NFPA 70 (NEC), NFPA 70E, IEEE, and international electrical codes.
• Excellent communication skills and ability to collaborate in a cross-discipline team.
• Comfortable with a fast-paced environment that is rapidly developing and changing.
• Prior experience with hyperscale data center environments or co-location facilities.

• Professional Engineering (PE) license or equivalent international certification (this position will not be stamping drawings as EOR).
• Previous experience designing for Tier III or Tier IV data centers as defined by Uptime Institute (or comparable levels of design).
• Visio, BlueBeam, AutoCAD, or other design and drafting software.

• Be part of a groundbreaking team influencing the next generation of data center systems!
• Collaborate with premier engineers and vendors to develop industry-leading AI hardware.
• Drive innovation in electrical design at scale with global impact.
• Access professional growth through sophisticated project involvement and multidisciplinary teamwork.
• Join a company committed to diversity and inclusion, where your work matters and drives global progress!

You will be working on accelerating ML across a variety of next generation Arm IP.

As part of this role, you will get to work on exciting projects related to functional and performance modeling and analysis - like modeling a new feature in our in-house models, workload characterization, analyzing performance, or developing tools on automation and visualization of the results.

• Functional or performance modeling experience for Hardware IP development
• Strong software development skills including experience with modern C++ and Python
• Strong problem solving and debugging skills
• Strong computer architecture and systems engineering fundamentals
• Good analysis and presentation skills
• Familiarity with Linux development

• Experience with Machine Learning IP development / systems
• Experience with cache-coherent memory system architecture
• Hardware microarchitecture exploration experience

As part of the methodology team, you will lead the development, improvement, and deployment of low power structural check methodologies across multiple SoC and IP projects. This role involves designing automated flows for UPF/CPF consistency, power domain integrity, and structural rule validation at both RTL and netlist levels. You will collaborate closely with design, verification, and EDA partners to ensure robust, scalable, and high-coverage power-aware design signoff strategies across technology nodes and product segments.

• Develop and maintain low-power structural check methodologies (UPF/CPF validation, isolation, level shifters, retention, domain crossings).
• Build automated flows using tools like Synopsys VC LP, SpyGlass-LP, and Conformal LP.
• Ensure power intent consistency and early issue detection through collaboration with design and verification teams.
• Integrate structural checks into signoff regressions with high coverage and low false positives.
• Work with vendors and internal teams to enhance tools, debug issues, and improve efficiency.
• Drive global adoption through documentation, training, and support.
• Assist in audits, quality reviews, and milestone checks.

• 5+ years of Strong background in low-power structural methodologies and UPF/CPF-based flows.
• Deep understanding of power intent specs, domain partitioning, isolation, and retention.
• Hands-on experience with tools like VC LP, SpyGlass-LP, or Cadence CLP.
• Skilled in scripting (Python, Perl, TCL) for flow automation.
• Experience with large SoC/IP designs across advanced nodes.
• Confirmed ability to debug structural issues and drive closure.
• Strong communication and documentation skills.

• Experience with formal verification or functional simulation for power-aware designs.
• Knowledge of complex power analysis and correlation with structural checks.
• Exposure to hierarchical low-power signoff strategies in multi-voltage or multi-power domain SoCs.
• Familiarity with power-aware DFT, scan strategies, and low-power aware synthesis flows.
• Participation in industry working groups (e.g., Accellera UPF), technical conferences, or publications.
• Involvement in tool benchmarking, vendor collaborations, and internal tool qualification projects.

We are proud to have a set of behaviors that reflects who we are and guides our decisions, defining how we work together to surpass ordinary and shape outstanding!

• Partner and dedication towards or customers
• Collaborate and communication
• Originality and resourcefulness
• Team and personal development
• Impact and influence
• Deliver on your promises