דרושים Senior Design Engineer ב-Arm ב-India, Bengaluru

Job Overview:

Responsibilities:

Required Skills and Experience:

We Prefer graduate or postgraduate from a university or Engineering School, in Electronic Engineering or equivalent Engineering Degree.

· You have 4-8 years of experience in SRAM/memory designs, margin analysis, characterization and verification

· You have some understanding of computer architecture and concepts.

· We expect you to have basic understanding of CMOS Transistors, their behaviors.

· We expect some basic understanding of high speed/low power CMOS circuit design, clocking scheme, static and complex logic circuits.

· Understanding of Power versus Performance versus Area trade-offs in typical CMOS design.

· You have an engineering demeanor and Passion for Circuit design.

· Expected to have good interpersonal skills.

“Nice To Have” Skills and Experience:

· You know basic scripting languages, e.g. Perl/TCL/Python.

· Some Experience of working on Cadence or Synopsys flows.

· Experience with Circuit Simulation and Optimization of standard cells.

· Silicon debug/validation

In Return:

• Proven 10+ years of experience in Quality Assurance and Test automation of product quality system software.
• Hands on experience of test code development and automation for firmware or system software. Excellent programming skills in C/C++.
• Python and Bash/Shell scripts are required.
• Good understanding of high-speed and low-speed IO protocols.: PCIe, DDR, I2C, SPI, SPMI, UART.
• Both pre-silicon and post-silicon Software/Firmware and system validation expertise.
• Good understanding of computer architecture, micro architecture concepts – ideally Arm architecture.
• Proficient with Git, Gitlab/Github API and version control scripting

• Experience in CI/CD, automation and software release
• Experience with Security Development Lifecycle (SDL) practices.
• Mentoring and line management experience

• Based in Bangalore India, this is an opportunity to join a dynamic, collaborative, and driven team, and provides a genuine opportunity to craft the best outcomes for Arm.
  

Responsibilities

• As a creative design engineer with a knowledge of subsystems and SoCs you will be part team developing Subsystems & SoCs.
• You will work with Architects to capture the requirements and develop Micro-architecture specifications for one or more SOC areas such as Power Management, Boot, Debug, Clocks, Resets, DDR, RAS, Security, Access Control, Die to Die etc.
• Key responsibilities will include writing micro-architecture and work with Design team to deliver high quality RTL.
• Collaborate with verification and Validation team to review test plans, and help debug design issues. Closely work with the Power and Performance analysis team to evaluate and improve Subsystem/SOC PPA.
• Contribute to developing and improving the design methodologies.
• Guide and support other members of the team for overall Program success. Balance other opportunities such as working with Project Management on activities, plans, and schedules

Required Skills and Experience:

• Bachelors or Master’s degree or equivalent experience in Electronics/Electrical Engineering.
• Experience of 8+ years working in design of complex compute subsystems or SoCs
• Expertise in developing Micro-architecture and Design specifications for the SoC Infrastructure areas such as Power Management, Boot, Debug, Clocks, Resets, DDR, RAS, Security, Access Control, Die to Die etc.
• Solid understanding of digital hardware design and Verilog HDL. Experience in development and Tapeout of Complex SoC and RTL Development.
• Experience leading and developing RTL for Subsystems or SoCs.
• Conversant with Lint, CDC and RDC flows.
• Good communication (written, verbal, presentations) skills.
• Experience with Perl, Python or other scripting language

Desired Skills and Experience:

• Experience with ARM-based designs and/or ARM System Architectures
• Experience developing subsystems for PCIe, LPDDR, HBM, UCIe, Ethernet
• Experience with SystemVerilog and verification methodologies – UVM/OVM
• Experience leading small teams or projects
• Experience or knowledge in the following areas
• Synthesis and timing analysis
• Static design checks, including CDC, RDC, X-Propagation, Linting
• Power management techniques
• DFT and physical implementation

As part of the methodology team, you will be responsible for developing and leading sophisticated power estimation and optimization methodologies at the netlist (gate-level) stage across SoC and IP designs. You will drive correlation strategies, automation flows, and accuracy improvements to ensure power estimates are tightly aligned with final silicon behavior. This role requires deep technical expertise in power analysis tools, a strong understanding of low-power design techniques, and collaboration with multi-functional teams across the design and verification cycle.

• Define and drive netlist-level power estimation methodologies using industry-leading tools (e.g., Synopsys PrimeTime PX, Cadence Voltus).
• Establish and maintain correlation frameworks between RTL and gate-level power, and between estimated and silicon power.
• Develop automated flows for toggling activity generation, vector-based and vectorless power estimation, and regression reporting.
• Analyze power consumption trends and identify hotspots; provide recommendations for low-power design optimization.
• Collaborate with RTL design, physical design, DFT, and architecture teams to ensure early and accurate power signoff.
• Lead methodology development for corner analysis, dynamic/static power separation, and voltage scaling assessments.
• Support signoff reviews, audits, and compliance to power specifications and constraints.
• Provide mentorship and technical leadership within the team and across global sites.

• Proven experience of 5+ years in power estimation, optimization, and methodology development at the gate-level/netlist stage.
• Hands-on expertise with tools such as Synopsys PrimeTime PX, Cadence Voltus, and related signoff flows.
• Strong understanding of digital design principles, low-power architecture techniques, clock gating, and multi-voltage domains.
• Proficient in scripting (Python, Perl, TCL) to develop scalable and automated power analysis flows.
• Demonstrated experience in analyzing switching activity data (SAIF/VCD/FSDB) and correlating to real application workloads.
• Confirmed ability to handle large SoC designs and deliver accurate power metrics under tight schedules.
• Excellent problem-solving skills, attention to detail, and ability to drive technical discussions and decisions.

• Experience with UPF/CPF power intent validation and integration.
• Exposure to thermal and IR-drop analysis in relation to power consumption.
• Familiarity with AI/ML-based power modeling or anomaly detection.
• Previous contributions to methodology deployment in domains such as mobile, automotive, or server-grade SoCs.
• Participation in EDA tool evaluations, benchmarking, and vendor teamwork.
• Publications or presentations in technical forums (e.g., SNUG, DVCon, DAC) related to power estimation or optimization.

We are proud to have a set of behaviors that reflects who we are and guides our decisions, defining how we work together to surpass ordinary and shape outstanding!

• Partner and dedication towards or customers
• Collaborate and communication
• Originality and resourcefulness
• Team and personal development
• Impact and influence
• Deliver on your promises

Job Overview:

We are seeking a motivated and skilled Software Engineer to join our innovative Media Tools team. In this role, you will be at the heart of developing and maintaining our Image Signal Processing (ISP) tools. The ideal candidate will have a strong background in C++ and is committed to creating high-quality and efficient code for our backend systems. While your primary focus will be on C++, you will also be expected to contribute to our JavaScript-based frontend as well participate in code reviews to maintain a high standard of code quality. This is a phenomenal opportunity for an eager engineer who is interested to contribute to the full stack of our outstanding imaging technology. As our team grows, there will be potential opportunities to expand your work into developing tools for Display Processing Units (DPUs) and Video Processing Units (VPUs).

Responsibilities:

• Design, develop, and optimize C++ algorithms for ISP
• Maintain and improve the existing C++ codebase for our imaging tools.
• Collaborate with the team to integrate backend and frontend components.
• Develop and improve user interfaces using JavaScript, HTML, and CSS.
• Work with our CI/CD pipelines using Jenkins to automate builds, testing, and deployments.
• Fix software defects and issues.

Required Skills and Experience:

• Strong proficiency in C++ development, particularly in a backend or algorithmic capacity.
• Motivation and ability to work on frontend tasks using JavaScript.
• Familiarity with continuous integration and continuous deployment (CI/CD) principles and experience with Jenkins.
• Thorough understanding of software development practices.

“Nice To Have” Skills and Experience:

• Familiarity with JavaScript frameworks (e.g., React, Vue, or Angular).
• Knowledge of version control systems, such as Git.
• Excellent problem-solving and analytical skills.
• Strong communication and teamwork abilities.

In Return:

As a Security Engineer – Fuzzing Specialist, you will own and evolve our coverage-guided fuzzing program. Your mission is to uncover hard-to-reach security flaws before attackers do, drive fixes to closure, and help product teams to embrace dynamic testing like fuzzing. You’ll scout for new attack surfaces, craft high-performance fuzzing harnesses, and design custom sanitisers that push the state of the art. Success means measurable coverage gains, actionable crash reports, and products that ship with provable resilience.

• Map & prioritise fuzzing surfaces across services, libraries, APIs, and protocols; maintain a living risk-based roadmap.
• Design, build, and extend fuzzing harnesses (libFuzzer, AFL++, Honggfuzz, etc.) that improve code-path exploration and minimise false positives.
• Continuously improve coverage by growing seed corpus, deploying targeted mutation strategies, and integrating new instrumentation techniques.
• Automate crash triage & root-cause analysis; distinguish exploitable vulnerabilities from benign faults and drive CVE-level findings to remediation.
• Develop custom sanitisers to expose classes of bugs traditional fuzzing misses.
• Validate fixes & guard against regressions through differential fuzzing and regression corpora.
• Assess external disclosures (bug bounties, supply-chain advisories) to determine fuzzing detectability and refine harnesses when gaps are found.
• Document, report, and share insights — from coverage metrics to post-mortems to create data-driven security.

• 1+ years in application or product security with a deep focus on coverage-guided fuzzing.
• Hands-on expertise with at least one modern fuzzing framework (e.g., libFuzzer, AFL++, Honggfuzz).
• Proficient in C/C++ plus strong scripting ability in Python for automation.
• Solid understanding of memory-safety vulnerabilities, undefined behaviour, sanitisers, and compiler instrumentation.
• Demonstrated ability to triage crashes using debuggers, profilers, and reverse-engineering tools (gdb/lldb, IDA/Ghidra).
• Excellent written communication for documenting findings and influencing engineering teams.

• Contributions to open-source fuzzing tools, sanitisers, or security research publications.
• Knowledge of distributed fuzzing at scale (GCP/AWS, Kubernetes, or bare-metal clusters).
• Familiarity with kernel, embedded, or firmware fuzzing (e.g., Syzkaller, QEMU-based harnesses).
• Background in reverse engineering, static analysis or symbolic execution.
• Experience integrating fuzzing into CI/CD pipelines and tracking coverage metrics.

• This role is for a DFT Engineer with 1 to 4 years of proven experience in Design for Test
• Experience coding in Verilog RTL, and scripting language like TCL, and/or Perl
• Proficient in Unix/Linux environments
• Core DFT skills considered crucial for this position should include some of the following: Scan compression and insertion, Memory BIST, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate-level verification, silicon debug
• Experience with Siemens, Cadence, and/or Synopsys DFT and simulation tools

• Familiarity with IEEE 1149, 1500, 1687
• Familiarity with Synthesis and Static Timing Analysis
• Working knowledge of Siemens DFT tools
• Ability to work both collaboratively on a team and independently.
• Innovative and a passion for progress
• Hard-working and excellent time management skills with an ability to multi-task

• Opportunity to work with some of the greatest minds in the industry!
• Competitive compensation and great benefits!
• Flexible working hours